Patent References 3508126 3717790 3745070 3771218 3793088 3880676 InventorAssigneeApplicationNo. 648593 filed on 01/12/1976US Classes:438/250, Planar capacitor257/398, Combined with heavily doped channel stop portion257/E21.147, By ion implantation (EPO)257/E21.285, Of silicon (EPO)257/E21.337, Through-implantation (EPO)438/522Including heat treatmentExaminersPrimary: Ozaki, G.Attorney, Agent or FirmInternational ClassH01L 021/26AbstractAn improved method of making N-channel, silicon gate, MOS integrated circuits such as used for memories is disclosed. Structural damage to the crystalline silicon such as caused by an ion implant process is reduced by a high temperature treatment in an inert atmosphere followed by oxidation. This treatment also alters the concentration profile of the implanted impurity to provide improved device characteristics. | |