Process for fabricating non-volatile field effect semiconductor memory structure utilizing implanted ions to induce trapping states
Patent 4047974 Issued on September 13, 1977. Estimated Expiration Date: 
September 13, 1994. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.
September 13, 1994. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent References 3328210 3500142 3877054 3878549 3895965 3906296 3922710 3925107 Switching device equipped with a semiconductor memory element Method of radiation hardening and gettering semiconductor devices InventorAssigneeApplicationNo. 05/645150 filed on 12/30/1975US Classes:438/288, Having step of storing electrical charge in gate dielectric257/324, Multiple insulator layers (e.g., MNOS structure)257/405, With gate insulator containing specified permanent charge257/406, Plural gate insulator layers257/E21.21, Comprising charge trapping insulator (EPO)257/E21.248, By ion implantation (EPO)257/E29.309, With charge trapping gate insulator (e.g., MNOS-memory transistors) (EPO)438/910CONTROLLING CHARGING STATE AT SEMICONDUCTOR-INSULATOR INTERFACEExaminersPrimary: Rutledge, L. DewayneAssistant: Saba, W. G. Attorney, Agent or FirmAbstractDisclosed is a non-volatile field effect information storage device which can be electrically written and erased. It consists of an insulated gate field effect transistor having a single gate dielectric material formed in two stages. The gate dielectric is made up of two adjacent layers of silicon dioxide, one of which is relatively thin and adjacent to the semiconductor substrate, while the other is relatively thick and implanted with ions at controlled depths and dosages near the interface with the first silicon dioxide layer. With the application of an appropriate control voltage on the gate structure, charges from the adjacent transistor channel region tunnel through the relatively thin layer of silicon dioxide and become stored in the trapping sites introduced by the implanted ions located in the second layer of silicon dioxide and very near the interface between the two silicon dioxide layers. While there, the charges control the conductivity of the channel, and thus the logic state of the transistor.Other References
| |
