Patent References 3741880 3798135 3864217 Method for fabricating electrode structure for a semiconductor device having a shallow junction Patent #: 3939047 InventorsAssigneeApplicationNo. 05/703412 filed on 07/08/1976US Classes:205/124, Predominantly nonmetal electrolytic coating (e.g., anodic oxide, etc.)257/750, Layered257/E21.291, By anodic oxidation (EPO)257/E21.585, Filling of holes, grooves, vias or trenches with conductive material (EPO)257/E21.592By altering solid-state characteristics of conductive members, e.g., fuses, in situ oxidation, laser melting (EPO)ExaminersPrimary: Tufariello, T. M.Attorney, Agent or FirmAbstractA method of making a multilevel conductor pattern for a semiconductor device. An aluminum layer on the substrate surface provides a situs for first level conductors. Successive soft and hard anodization steps are advantageously used to provide excellent intralevel isolation and interlevel electrical connection in desired areas. First level conductor sites are masked and the two anodized films are selectively removed in the desired nonconductive areas. The remaining first level aluminum is completely anodized. An insulating layer is then deposited and vias are formed therethrough to connect a subsequently deposited second level metallization layer with the conductor sites. |
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