Planarization of integrated circuit surfaces through selective photoresist masking
Patent 4038110 Issued on July 26, 1977. Estimated Expiration Date: 
July 26, 1994. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.
July 26, 1994. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent References 3681153 3783047 3883889 Method for forming recessed dielectric isolation with a minimized "bird's beak" problem Method for forming dielectric isolation combining dielectric deposition and thermal oxidation Patent #: 3966514 InventorAssigneeApplicationNo. 05/696102 filed on 06/14/1976US Classes:438/552, Having plural predetermined openings in master mask257/519, Including heavily doped channel stop region adjacent groove257/626, Combined with passivating coating257/639, At least one layer of silicon oxynitride257/640, At least one layer of silicon nitride257/E21.033, Comprising inorganic layer (EPO)257/E21.242, Of organic layer (EPO)257/E21.245, Removal by chemical etching, e.g., dry etching (EPO)257/E21.246, Removal by selective chemical etching, e.g., selective dry etching through mask (EPO)257/E21.251, By chemical means (EPO)257/E21.258, Using masks (EPO)257/E21.466, Diffusion of impurity material, e.g., dopant, electrode material, into or out of semiconductor body, or between semiconductor regions (EPO)257/E21.548, Concurrent filling of plurality of trenches having different trench shape or dimension, e.g., rectangular and V-shaped trenches, wide and narrow trenches, shallow and deep trenches (EPO)257/E21.549, Of trenches having shape other than rectangular or V shape, e.g., rounded corners, oblique or rounded trench walls (EPO)438/359, Dielectric isolation formed by grooving and refilling with dielectrical material438/433, Dopant addition438/556, Edge diffusion by using edge portion of structure other than masking layer to mask438/698Utilizing reflowExaminersPrimary: Rutledge, L. DewayneAssistant: Davis, J. Attorney, Agent or FirmAbstractAn integrated circuit substrate surface, particularly a surface of electrically insulative material, having a pattern of elevated areas and a complementary pattern of unelevated areas is planarized by forming the photoresist pattern in registration with the pattern of unelevated areas, the photoresist pattern having narrower lateral dimensions than said elevated pattern whereby registration is facilitated, flowing the photoresist pattern to laterally expand the photoresist to cover and thereby mask the unelevated areas, and etching to lower the elevated area which remain uncovered by the photoresist. | |
