Interpolation-decimation circuit for increasing or decreasing digital sampling frequency
Patent 4020332 Issued on April 26, 1977. Estimated Expiration Date: 
April 26, 1994. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.
April 26, 1994. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent References 3829670 3872290 InventorsAssigneeApplicationNo. 05/616283 filed on 09/24/1975US Classes:708/290, Interpolation/extrapolation341/61, Data rate conversion708/313Decimation/interpolationExaminersPrimary: Malzahn, David H.Attorney, Agent or FirmAbstractA general purpose interpolator-decimator circuit for increasing or decreasing the sampling rate of a digital signal by a factor L/M, where L and M are integers, is disclosed. The circuit includes means for determining each output sample by multiplying a sequence of previous input samples by a set of coefficients and accumulating the resulting products. L sets of coefficients, in which each coefficient is a function of the factors L and M, are stored in a specific sequence which permits sequential addressing of both the coefficients and input signal samples. A multistage decimator cascaded with a multistage interpolator to effect a narrow-band FIR filter is also disclosed.Other References
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