U.S. patents available from 1976 to present.
U.S. patent applications available from 2005 to present.

Digital video synchronizer

Patent 4018990 Issued on April 19, 1977. Estimated Expiration Date: Icon_subject April 19, 1994. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.

Patent References

3763317

3795763

3906367

Inventors

Assignee

Application

No. 05/549571 filed on 02/13/1975

US Classes:

348/513, Frame or field synchronizers348/506, Burst gate348/571, IMAGE SIGNAL PROCESSING CIRCUITRY SPECIFIC TO TELEVISION386/18Using variable delay

Examiners

Primary: Morrison, Malcolm A.
Assistant: Krass, Errol A.

Attorney, Agent or Firm

Abstract

A method and apparatus for synchronizing unrelated video type signals from two different sources without employing feedback loops between the two sources.Incoming video signals are converted from analog to digital form and are clocked into a shift register unit by input clock signals phase and frequency locked to the instantaneous horizontal frequency and the color burst frequency portions of the incoming signal. The digitized video signals progressing along the shift register are stored at the input clock signal rate in a random access (RAM) having a sufficient capacity to provide continuous output video signals during each field. The signals are clocked out from the RAM by output clock signals derived from the sync and color burst portions of a local signal comprising either composite video or composite color burst, which are synchronized with the local sync generator. The video signals fetched from the RAM are converted from digital to analog form by the output clock signals, are processed to include standard sync, blanking and color burst signals, and are coupled to follow-on equipment.The sync burst portions of the incoming non-synchronized video signals are deleted during storage in the shift register so that a smaller shift register can store an entire video field. The shift register has a plurality of output taps providing different coarse delay periods only one of which is enabled by a vertical sync pulse in the output clock train prior to transfer of a given field into the RAM.

PatentsPlus Images
Enhanced PDF formats
loading...
PatentsPlus: add to cart
PatentsPlus: add to cartSearch-enhanced full patent PDF image
$9.95more info
PatentsPlus: add to cart
PatentsPlus: add to cartIntelligent turbocharged patent PDFs with marked up images
$18.95more info
 
Sign InRegister
Username  
Password   
forgot password?