Processes of forming insulated gate field effect transistors with channel lengths of one micron in integrated circuits with component isolated and product
Patent 3996655 Issued on December 14, 1976. Estimated Expiration Date: 
December 14, 1993. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.
December 14, 1993. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent References3766446 InventorsAssigneeApplicationNo. 607526 filed on 08/25/1975US Classes:438/279, Making plural insulated gate field effect transistors having common active region257/335, Active channel region has a graded dopant concentration decreasing with distance from source region (e.g., double diffused device, DMOS transistor)257/E21.544, PN junction isolation (EPO)257/E27.06, Field-effect transistor with insulated gate (EPO)438/285, Utilizing compound semiconductor438/286, Asymmetric438/294Including isolation structureExaminersPrimary: Tupman, W.Attorney, Agent or FirmAbstractThe disclosure relates to methods of forming Insulated Gate Field Effect transistors and the product suitable for integrated circuits with channel lengths of 1 micron or less, the transistors being isolated from other transistors or other components in the circuit without the requirements of extra isolation steps. This is provided by means of a double diffusion which isolates the channel of the transistor from other elements in the circuit. Channel length is solely a function of the diffusion schedule through openings in the oxide through which the double diffusion takes place. | |
