ApplicationNo. 607526 filed on 08/25/1975
US Classes:438/279, Making plural insulated gate field effect transistors having common active region257/335, Active channel region has a graded dopant concentration decreasing with distance from source region (e.g., double diffused device, DMOS transistor)257/E21.544, PN junction isolation (EPO)257/E27.06, Field-effect transistor with insulated gate (EPO)438/285, Utilizing compound semiconductor438/286, Asymmetric438/294Including isolation structure
ExaminersPrimary: Tupman, W.
Attorney, Agent or Firm
AbstractThe disclosure relates to methods of forming Insulated Gate Field Effect transistors and the product suitable for integrated circuits with channel lengths of 1 micron or less, the transistors being isolated from other transistors or other components in the circuit without the requirements of extra isolation steps. This is provided by means of a double diffusion which isolates the channel of the transistor from other elements in the circuit. Channel length is solely a function of the diffusion schedule through openings in the oxide through which the double diffusion takes place.