Patent References 3403284 3458782 3507709 3717790 3810796 3852120 3886530 InventorsAssigneeApplicationNo. 05/553717 filed on 02/27/1975US Classes:257/461, Light responsive pn junction257/917, PLURAL DOPANTS OF SAME CONDUCTIVITY TYPE IN SAME REGION257/E21.248, By ion implantation (EPO)257/E29.016, For preventing surface leakage due to surface inversion layer (e.g., channel stop) (EPO)257/E29.255, With field effect produced by insulated gate (EPO)257/E31.119, Coatings (EPO)257/E31.12, For device having potential or surface barrier (EPO)313/367MosaicExaminersPrimary: Edlow, Martin H.Attorney, Agent or FirmInternational ClassesH01J 29/45 (20060101)H01L 29/78 (20060101) H01J 29/10 (20060101) H01L 29/06 (20060101) H01L 29/00 (20060101) H01L 29/02 (20060101) H01L 21/02 (20060101) H01L 21/3115 (20060101) H01L 21/00 (20060101) H01L 31/00 (20060101) H01L 31/0216 (20060101) H01L 29/66 (20060101) H01L 27/00 (20060101) AbstractA semiconductor structure having a surface insulating layer formed as a grid with charges implanted in the insulating material to prevent inversion and, hence, channeling between adjacent semiconductor regions, preferably for use in a non-blooming vidicon. The method of manufacturing such a structure uses ion implantation to create immobile positive charges in a grid pattern in an insulating layer in regions spaced from the interface between the insulating layer and the semiconductor body. The insulating layer is of sufficient thickness that substantially all of the charge sites in the insulating layer are separated from the outer surface of the insulator by a sufficient distance to effectively prevent a negative electric field from reaching into the silicon. | |