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US Patent 3953808 - Solid state amplifier

US Patent Issued on April 27, 1976
Estimated Patent Expiration Date: Icon_subject April 27, 1993Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.
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Abstract

A solid state amplifier includes at least one junction field effect transistor and an impedance network coupled between a signal input terminal of the amplifier and a gate terminal of the transistor. The network includes a p-n junction device having a region of conductivity opposite to that of the gate of the transistor coupled to the gate terminal, the p-n junction being shunted by a resistor coupled in parallel therewith. The network minimizes signal distortion which would otherwise be introduced to the signal output of the amplifier when an inductive load is present in the output circuit of the amplifier.

Other References

  • Compton-"Designing with FETs in Cascode"- Edn Magazine, Sept. 14, 1966
  • "Cascode Stage Using FETs"-Electronic Design, Vol. 12, p. 76, May, 1964
  • Holt et al., "Hybrid Integrated Networks"- The Western Electric Engineer, Jan. 1975

Inventors

Assignee

Application

No. 572577 filed on 04/28/1975

US Classes:

330/277, Including field effect transistor315/52, Plural impedance elements327/581, Field-effect transistor327/586, Capacitive diode330/296Including particular biasing arrangement

Examiners

Primary: Rolinec, R. V.
Assistant: Dahl, Lawrence J.

Attorney, Agent or Firm

US Patent References

2618690, 3325654, 3351654, 3501806, 3742261, 3757245, 3767946

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