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| Number | Title | Issue Date |
| 6470465 | Parallel test circuit of semiconductor memory device A parallel test circuit for a semiconductor memory device includes a divided output driver configuration capable of generating a tri-state output. The parallel test circuit has a main output driver for outputting a signal having a first level when cell ar... | 10/22/2002 |
| 6470466 | Integration type input circuit and method of testing it An input interface circuit is provided. The circuit includes an input transistor for receiving a digital input signal, a circuit for generating a reference value, and an integrating capacitor connected in series to a pair of current conducting electrodes ... | 10/22/2002 |
| 6470467 | Synchronous semiconductor memory device capable of performing operation test at high speed while reducing burden on tester A driver circuit applies a write data whose level is inverted for every write cycle to a selected memory cell in accordance with a write data held by a latch circuit when a writing operation in a test operation mode is designated in the test operation mod... | 10/22/2002 |
| 6470468 | Test pattern generator, propagation path disconnecting method, and delay fault detecting method A test pattern generator for automatically generating a test pattern for detecting a stack fault of a large scale integrated circuit an LSI with a tester includes a loop/path disconnecting section for disconnecting a loop portion of the LSI at a position ... | 10/22/2002 |
| 6470469 | Reconstruction of missing coefficients of overcomplete linear transforms using projections onto convex sets A projection onto convex sets (POCS)-based method for consistent reconstruction of a signal from a subset of quantized coefficients received from an N×K overcomplete transform. By choosing a frame operator F to be the concatenization of two or more K×K ... | 10/22/2002 |
| 6470470 | Information coding method and devices utilizing error correction and error detection Focused error correction and/or focused error detection is used in the information coding system. A speech encoding method, in which the number of speech parameter bits on which error correction coding and/or error detection coding focuses is automaticall... | 10/22/2002 |
| 6470471 | Data error correction apparatus A data error correction apparatus includes sixteen units of syndrome calculators for calculating syndromes of one code word of an octuple error correcting Reed-Solomon code, and these calculators comprise Galois field adders, flip-flops, and first constan... | 10/22/2002 |
| 6470472 | Arrangements and method relating to transmission of digital data A receiving arrangement receives digitally coded data signals transported over a channel. The data signal includes sequences divided into blocks, and the receiving arrangement includes an error correcting device providing a number of alternative blocks, a... | 10/22/2002 |
| 6470473 | Data decoding processing system and method A DVD-ROM data decoding processing system includes a DVD-ROM reproducing unit 32 and a buffer memory 34. The DVD-ROM reproducing unit 32 includes a demodulating part 36, a PI syndrome generating part 38, an error correcting part 40, a buffer memory 42 hav... | 10/22/2002 |
| 6470474 | Method and apparatus for identifying errors in a detected sequence of values A method and apparatus are provided for identifying errors in a detected sequence of values generates the detected sequence of values from channel samples using a detector designed for a channel with a first channel response characteristic. The detected s... | 10/22/2002 |
| 6470475 | Synthesizable synchronous static RAM A synthesizable, synchronous static RAM may include custom built memory cells and a semi-custom input/output/precharge section in bit slice form, a semi-custom built decoder connected to the bit slice, and a semi-custom built control clock generation sect... | 10/22/2002 |
| 6470476 | Substitution of non-minimum groundrule cells for non-critical minimum groundrule cells to increase yield A structure and method for improving yield during physical chip design comprises identifying non-critically timed minimum groundrule cells located within the chip design, determining if whitespace exists around the non-critically timed minimum groundrule ... | 10/22/2002 |
| 6470477 | Methods for converting features to a uniform micron technology in an integrated circuit design and apparatus for doing the same A method for converting physical features of an integrated circuit design to a uniform micron technology is provided. The integrated circuit design is defined by a plurality of cells with each cell being defined by one or more micron technologies. A user ... | 10/22/2002 |
| 6470478 | Method and system for counting events within a simulation model A method and system that utilize the expressiveness of hardware description languages for efficiently and comprehensively monitoring performance characteristics of a digital circuit design during simulation. According to the present invention, a design en... | 10/22/2002 |
| 6470479 | Method of verifying semiconductor integrated circuit reliability and cell library database A method of verifying semiconductor integrated circuit reliability allows reliability verification of a large-scale semiconductor integrated circuit without any omission. Step S12 is to obtain a sum total (Cio) of inner-cell input/output load capacities i... | 10/22/2002 |
| 6470480 | Tracing different states reached by a signal in a functional verification system A functional verification system which provides information as to whether a signal has reached all possible states. For example, in the case of a signal with 0 and 1 as possible states, a 2 bit variable is initialized to 00. When a value of 1 is received ... | 10/22/2002 |
| 6470481 | State management in a co-verification system A method and apparatus for state management in a co-verification system is described. The invention allows acceleration of co-simulation without loss of information that can occur from independent simulation of software and hardware components of a design... | 10/22/2002 |
| 6470482 | METHOD AND SYSTEM FOR CREATING, DERIVING AND VALIDATING STRUCTURAL DESCRIPTION OF ELECTRONIC SYSTEM FROM HIGHER LEVEL, BEHAVIOR-ORIENTED DESCRIPTION, INCLUDING INTERACTIVE SCHEMATIC DESIGN AND SIMULATION A system for interactive design, synthesis and simulation of an electronic system allowing a user to design a system either by specification of a behavioral model in a high level language such as VHDL or by graphical entry. The user can view full or parti... | 10/22/2002 |
| 6470483 | Method and apparatus for measuring internal clock skew An integrated circuit for measuring internal clock skew is provided. The integrated circuit includes a first controlled delay module, which is operable to receive one of a sampling clock signal and a sampled clock signal. The integrated circuit further in... | 10/22/2002 |
| 6470484 | System and method for efficient layout of functionally extraneous cells A method for defining electrical components enables a layout tool to include functionally extraneous cells in an integrated circuit design without significant adverse impact to the operation of the logically functional cells. The method defines the descri... | 10/22/2002 |
| 6470485 | Scalable and parallel processing methods and structures for testing configurable interconnect network in FPGA device Configurable interconnect resources of field programmable gate arrays (FPGA's) are tested by configuring at least some of the lookup tables (LUT's), registers and input signal acquirers to implement one or more sequential state machines that feed back the... | 10/22/2002 |
| 6470486 | Method for delay-optimizing technology mapping of digital logic A delay-optimizing technology-mapping process for an electronic design automation system selects the best combination of library devices to use in a forward and a backward sweep of circuit trees representing a design. A technology selection process in an ... | 10/22/2002 |
| 6470487 | Parallelization of resynthesis A method for resynthesizing a design of an integrated circuit using a parallel processing mode. A single processing mode is entered by activating a main thread and locking a semaphore associated with the main thread. The design of the integrated circuit i... | 10/22/2002 |
| 6470488 | Method for manufacturing a mask The present invention provides a method of manufacturing an mask. An integrated circuit layout data base is first provided, which includes N+ ion implantation layout data, P+ ion implantation layout data, defined polysilicon layout d... | 10/22/2002 |
| 6470489 | Design rule checking system and method A method for performing design rule checking on OPC corrected or otherwise corrected designs is described. This method comprises accessing a corrected design and generating a simulated image. The simulated image corresponds to a simulation of an image whi... | 10/22/2002 |
| 6470490 | Contextual data representation and retrieval method A method for information representation and retrieval within a general-purpose digital computer. Information of all simple types is represented as points along dimensions, and compound information types are represented as the intersection of two or more d... | 10/22/2002 |
| 6470491 | Method for monitoring computer programs on window-based operating platforms This invention relates to a method for monitoring an executed process, more particularly for monitoring and tracing the execution of an application program on a window-based operating platform. The method of the present invention is first to collect the i... | 10/22/2002 |
| 6470492 | Low overhead speculative selection of hot traces in a caching dynamic translator A method and apparatus for selecting hot traces for translation and/or optimization is described in the context of a caching dynamic translator. The code cache stores hot traces. Profiling is done at locations that satisfy a start-of-trace condition, e.g.... | 10/22/2002 |
| 6470493 | Computer method and apparatus for safe instrumentation of reverse executable program modules Computer method and apparatus allows instrumentation of program modules while maintaining exception-handling unwinding context. In the case of instrumenting procedure prologues, the invention preserves the calling context. A sanitized copy of the prologue... | 10/22/2002 |
| 6470494 | Class loader This invention relates to the loading of classes in programming environments, and in particular, Java programming environments. This invention discloses a system and method that permits dynamic loading of classes during the execution of Java programs. Thi... | 10/22/2002 |
| 6470495 | Satellite control of electronic memory devices Microprocessor-controlled equipment, such as cash register/inventory control systems, sometimes require in-field modification of programs which run on the microprocessors. Under the invention, such modified programs are downloaded to the equipment, via a ... | 10/22/2002 |
| 6470496 | Control program downloading method for replacing control program in digital broadcast receiving apparatus with new control program sent from digital broadcast transmitting apparatus To provide a control program downloading method that is used by a digital broadcast receiving apparatus equipped with a storing device which stores an update program and a non-update program that compose a control program. Under control of the update prog... | 10/22/2002 |
| 6470497 | Electronic television program guide schedule system and method with scan feature An electronic program schedule system which utilizes a receiver for receiving broadcast, satellite or cablecast television programs for a plurality of television channels and a tuner for tuning a television receiver to a selected one of the plurality of c... | 10/22/2002 |
| 6470498 | Personal computer system, compact disk and method for interactively viewing the earth Abstract of the Disclosure A method of interactively viewing the Earth including the steps of: selecting satellite viewpointd of a region of the Earth; reading prestored imaged of the region of the Earth from the satellite viewpointd; displaying the prest... | 10/22/2002 |
