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A method of swing on a swing is disclosed, in which a user positioned on a standard swing suspended by two chains from a substantially horizontal tree branch induces side to side motion by pulling alternately on one chain and then the other.
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| Number | Title | Issue Date |
| 6192486 | Memory defect steering circuit The present invention provides a method and system for bypassing defective sections with a memory array of a computer chip. The circuit in accordance with the present invention includes a register for controlling the effective size of the memory array bas... | 02/20/2001 |
| 6192487 | Method and system for remapping physical memory A method and system for remapping physical memory that is malfunctioning. The physical memory has memory locations with addresses. The addresses are ordered from a lowest to a highest address, and each address has bits ordered from a highest-order bit to ... | 02/20/2001 |
| 6192488 | Restoring method for hard disk Disclosed is a restoring method for hard disk comprising following steps: scanning the partition and file allocation table (FAT) of hard disk and recording above information in a plurality of flag regions on end portion of hard disk wherein each flag regi... | 02/20/2001 |
| 6192489 | Fault tolerant design for identification of AC defects including variance of cycle time to maintain system operation A mechanism for handling processing errors in a computer system. The mechanism includes a first means for processing a stream of instructions, second means for detecting an error caused by a timing dependant defect and occurring during processing of the i... | 02/20/2001 |
| 6192490 | Method and system for monitoring computer performance utilizing sound diagnostics A method and system for diagnosing data-processing system performance. Initially, unique audible sounds are associated with particular performance indicators within the data-processing system. Thereafter, performance indicators are identified, one or more... | 02/20/2001 |
| 6192491 | Data processor with CRC instruction set extension A programmable data communications device is provided to process multiple streams of data according to multiple protocols. The device is equipped with a co-processor including multiple, programmable processors allowing data to be operated on by multiple p... | 02/20/2001 |
| 6192492 | Fast ATA-compatible drive interface with error detection and/or error correction An ATA-compatible drive interface with error correction and detection capabilities is disclosed. Being fully ATA backward compatible, this interface functions with the same physical cable and connectors as current ATA systems, employs bus drivers that are... | 02/20/2001 |
| 6192493 | Data element interleaving/deinterleaving To interleave or deinterleave data elements in first and second blocks transmitted alternately and each having N data elements with rank n lying between 0 and N-1, N being an integer, the data elements with ranks 0, . . . n, . . . N-1 in the first blocks ... | 02/20/2001 |
| 6192494 | Apparatus and method for analyzing circuit test results and recording medium storing analytical program therefor An intelligence data base 23 stores interconnection information and position information on the basis of a substrate about a decoder for an LSI memory cell and memory cells and further stores a program for judging whether the memory cell regarded as defec... | 02/20/2001 |
| 6192495 | On-board testing circuit and method for improving testing of integrated circuits A system allowing testing a plurality of integrated circuits mounted on a common substrate is described. The testing system includes a failure processor mounted on the substrate. The substrate has a first signal port adapted to be coupled to a testing dev... | 02/20/2001 |
| 6192496 | System for verifying signal timing accuracy on a digital testing device An apparatus and method are provided for testing component tolerances of a device for testing integrated circuits. The testing device is generally characterized by a plurality of test connectors disposed at a test head, wherein each test connector carries... | 02/20/2001 |
| 6192497 | Parallel Chien search circuit Disclosed is a Chien search circuit for determining roots to an error locator polynomial that is defined by a set of coefficients. The circuit includes N sub-Chien search circuits, each of which is configured to sequentially evaluate a subset of field ele... | 02/20/2001 |
| 6192498 | System and method for generating error checking data in a communications system A circuit and method for generating cyclic redundancy check (CRC) data is disclosed. In one embodiment, the circuit interfaces with a data bus with other processor components. The circuit includes an input first-in-first-out (FIFO) to interface with the d... | 02/20/2001 |
| 6192499 | Device and method for extending error correction beyond one sector time Disclosed is an error detection and correction device for extending error correction time on a data sector beyond the time to receive a next data sector. The error detection and correction device is coupled to sequentially receive a plurality data sectors... | 02/20/2001 |
| 6192500 | Method and apparatus for enhanced performance in a system employing convolutional decoding The invention comprises a method and apparatus for decoding an incoming symbol stream comprised of a plurality of known missing symbols. Within the incoming symbol stream, those symbols corresponding the known missing symbols are replaced with a first set... | 02/20/2001 |
| 6192501 | High data rate maximum a posteriori decoder for segmented trellis code words In a communications system, a trellis code word is segmented by both the encoder and a segmented MAP decoder. The segmented MAP decoder operates on code word segments as if they were individual code words and takes advantage of knowing the state of the en... | 02/20/2001 |
| 6192502 | Information reproducing apparatus and reproducing method In a Viterbi decoder, an SMU is used instead of a PMU. The SMU has four status memories that process a status data value composed of a plurality of bits that represent a status at a time. The status memories generate a sequence of four status data values.... | 02/20/2001 |
| 6192503 | Communications system and methods employing selective recursive decording A source sequence of symbols is communicated over a communications medium by encoding the source sequence according to respective first and second error correction codes to produce respective first and second encoded sequences of symbols. The first and se... | 02/20/2001 |
| 6192505 | Method and system for reducing state space variables prior to symbolic model checking A computer-implemented method for systematically eliminating redundant circuit elements in a state machine of a model having sequential circuit elements possessing one of a fixed number of possible states, typically "0" and "1". Initially, the sequential ... | 02/20/2001 |
| 6192506 | Controller for solving logic A logic controller includes a memory for storing representations of boolean logic. The boolean logic includes AND and OR boolean logic functions having target values and a plurality of inputs. The processor of the logic controller has input/output circuit... | 02/20/2001 |
| 6192507 | Method for generating an electrical circuit comprising dielectrics A method comprising a computational procedure for obtaining capacitances for three-dimensional geometries which include multiple regions with different dielectric constants. The methodology is not limited to uniform dielectrics. The dielectric regions can... | 02/20/2001 |
| 6192508 | Method for logic optimization for improving timing and congestion during placement in integrated circuit design This invention recognizes the ability of logic optimization to help placement relieve congestion. Different types of logic optimizations are used to help placement relieve congestion. In one type of optimization, the speed of parts of the circuit is impro... | 02/20/2001 |
| 6192509 | Method and apparatus for automatically removing acid traps from a hatched fill in a printed circuit board design The present invention beneficially provides a method and apparatus for automatically removing acid traps from a hatched fill in a printed circuit board design. The printed circuit board design includes a cross-hatched fill area comprising boundary lines a... | 02/20/2001 |
| 6192510 | Method of preparing a partial one-shot electron beam exposure mask and method of direct-writing patterns by use of a partial one-shot electron beam exposure mask A method of extracting data of at least one aperture mask pattern from design data which includes write-required patterns and repeating units, so that boundary lines of the at least one aperture mask pattern are different from boundary lines of the repeat... | 02/20/2001 |
| 6192511 | Technique for test coverage of visual programs A method, system, and computer program for providing test coverage metrics in a visual programming environment. A test coverage model for visual programming is defined, which accounts for the specialized nature of visual programming, and the metrics are b... | 02/20/2001 |
| 6192512 | Interpreter with virtualized interface A computer application program subsystem (100) includes a program interpreter (120) and an application program interface (API 110) through which an external program requests an execution of a program of interest, such as a macro, in a specified simulated ... | 02/20/2001 |
| 6192513 | Mechanism for finding spare registers in binary code The inventive system and method determines the availability of spare registers in binary code for use by an instrument or program by conducting a local search of either the immediate block of program code or of successor blocks, depending upon where instr... | 02/20/2001 |
| 6192514 | Multicomputer system A method is provided for responding to a computer system call requesting creation of such new process in a multicomputer system which includes multiple sites, each site including a local processor and local memory, and wherein the multicomputer system inc... | 02/20/2001 |
| 6192515 | Method for software pipelining nested loops A method for software pipelining nested loops combines the inner and outer loops of the nested loop to form a merged loop. One or more operations from the outer loop are activated on selected passes through the merged loop, and the merged loop is software... | 02/20/2001 |
| 6192517 | Method, apparatus, and product for improved garbage collection in a memory system through the removal of reference conflicts In accordance with the present invention a method for modifying a sequence of instructions to improve memory management within a storage device during execution of the instructions, comprises the steps, performed by a processor, of (a) analyzing the seque... | 02/20/2001 |
| 6192518 | Method for distributing software over network links via electronic mail The present invention discloses a method, apparatus, and article of manufacture for distributing a software application residing on a network, from a source computer coupled to the network, to a remote computer via electronic mail. At the source computer,... | 02/20/2001 |
