Celebrity Inventors
Comic actor Danny Kaye received patent D166,807 for the co-design of "Blowout Toy or the Like". It's similar to one of those toys that unravels when you blow into at a birthday party except Kaye's has three blowouts going in different directions, not just one.
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| Number | Title | Issue Date |
| 6076154 | VLIW processor has different functional units operating on commands of different widths A VLIW processor has first and second functional units for executing first and second commands in a first instruction word. The first and second commands comprise a first field and a second field, respectively, in ordered concatenations of fields. The pro... | 06/13/2000 |
| 6076155 | Shared register architecture for a dual-instruction-set CPU to facilitate data exchange between the instruction sets A dual-instruction set central processing unit (CPU) is capable of executing instructions from a reduced instruction set computer (RISC) instruction set and from a complex instruction set computer (CISC) instruction set. Data and address information may b... | 06/13/2000 |
| 6076156 | Instruction redefinition using model specific registers A microprocessor employs an instruction redefinition register which programmably redefines the operation performed by one or more instructions. Instructions may be added to the instruction set executed by the microprocessor without consuming opcode encodi... | 06/13/2000 |
| 6076157 | Method and apparatus to force a thread switch in a multithreaded processor A system and method for performing computer processing operations in a data processing system includes a multithreaded processor and thread switch logic. The multithreaded processor is capable of switching between two or more threads of instructions which... | 06/13/2000 |
| 6076158 | Branch prediction in high-performance processor A CPU of the RISC type employs a standardized, fixed instruction size, and permits only simplified memory access data width and addressing modes limited to register-to-register operations and register load/store operations. Byte manipulation instructions ... | 06/13/2000 |
| 6076159 | Execution of a loop instructing in a loop pipeline after detection of a first occurrence of the loop instruction in an integer pipeline A data processor is disclosed which comprises a first pipeline for decoding and executing data instructions, a second pipeline for decoding and executing address instructions, a unit for issuing multiple instructions to the pipelines, a first set of regis... | 06/13/2000 |
| 6076160 | Hardware-based system for enabling data transfers between a CPU and chip set logic of a computer system on both edges of bus clock signal A hardware-based system for configuring a CPU and chip set logic of a computer system to allow data transfers on both the rising and falling edges of a bus clock signal. The CPU and chip set logic each include bus communication circuitry for transferring ... | 06/13/2000 |
| 6076161 | Microcontroller mode selection system and method upon reset A system and method for selecting a post-reset operating mode for a microcontroller. The system of this invention includes a mode indicating means to communicate to the microcontroller the desired post-reset operating mode. These means may include pin(s),... | 06/13/2000 |
| 6076162 | Certification of cryptographic keys for chipcards The invention relates to a procedure for the certification of cryptographic keys for use in chipcards. In this procedure, a certification key and a certificate are transferred to the chipcard. The first part of the certificate includes the cryptographic k... | 06/13/2000 |
| 6076163 | Secure user identification based on constrained polynomials Methods and apparatus for providing secure user identification or digital signatures based on evaluation of constrained polynomials. In an exemplary user identification technique, a prover sends a verifier a commitment signal representative of a first pol... | 06/13/2000 |
| 6076164 | Authentication method and system using IC card A method and system for authenticating between a user or client and a network access entity such as a server or another client using an IC card. The method includes a step of executing an initial authentication using the IC card when the user first commun... | 06/13/2000 |
| 6076165 | Method for authenticating digital recording devices A method for authenticating digital storage devices, including compact discs, CD-Roms, DVDs and floppy discs, is provided. A predetermined "fingerprint" code is embedded in one or more of the parity bytes which are always appended to the end of data frame... | 06/13/2000 |
| 6076166 | Personalizing hospital intranet web sites The server includes a layer for dynamically generating web pages and other data objects using scripts, such as graphic, audio and video files, in dependence on stored information indicating the user's needs and preferences, including those presumed from s... | 06/13/2000 |
| 6076167 | Method and system for improving security in network applications A method of enhancing network security is provided for a communication session initiated between a first computer and a second other computer. From the first computer to the second computer in communications therewith a process for securing communications... | 06/13/2000 |
| 6076168 | Simplified method of configuring internet protocol security tunnels A method of securing data traffic between a local and remote host systems is provided. The method includes autogenerating a filter having rules associated with a defined tunnel. The filter rules are used to permit or deny acceptance of transmitted data by... | 06/13/2000 |
| 6076169 | Computer system having a screen saver with a power shutdown function and a control method thereof This invention relates to a computer system having a screen saver with a power shutdown function and the control method thereof, comprising a timer for measuring time, an input device for inputting, and a controller for automatically terminating an operat... | 06/13/2000 |
| 6076170 | Method and apparatus for selectively programming access time in a data processor In a data processing system, a memory control unit (22) provides a control register bit field (60), logic, and a state machine (62) which facilitate a programmable number of clocks for an initial access to an on-chip memory (20). Specifically, the memory ... | 06/13/2000 |
| 6076171 | Information processing apparatus with CPU-load-based clock frequency An information processing apparatus includes a CPU, a memory, and a reference signal generator and operates based on a system clock signal generated by the reference signal generator. The apparatus includes a detection unit for detecting a CPU operational... | 06/13/2000 |
| 6076172 | Monitoting system for electronic control unit Accompanied by turning on power, power ON reset pulse from a power ON reset generation circuit is input to CPU and a fail determining circuit. After receiving the power ON reset pulse, the fail determining circuit intentionally outputs a fail detection si... | 06/13/2000 |
| 6076173 | Architectural coverage measure A tractable architecture level coverage measure uses information about the coverage measures obtained by the data path blocks, control logic blocks and cache to obtain an overall measure of coverage. This technique is applicable to a variety of different ... | 06/13/2000 |
| 6076174 | Scheduling framework for a heterogeneous computer network A scheduling framework for a heterogeneous computer network comprises a task performance predictor for estimating computation time on each computer in a network for each job input to the network, a performance characteristics database for recording inform... | 06/13/2000 |
| 6076175 | Controlled phase noise generation method for enhanced testability of clock and data generator and recovery circuits A transmitter/receiver chip includes circuitry for testing the bit error rate of the chip. A controlled amount of noise is introduced to the chip to vary a timing parameter of a transmit clock, resulting in an increase in a bit error rate of the chip. Art... | 06/13/2000 |
| 6076176 | Encoding of failing bit addresses to facilitate multi-bit failure detect using a wired-OR scheme A technique for encoding failing bit addresses in a memory array with redundant portions such as column slices. The address or other identification of a column slice or other portion of a memory array is identified to test logic using a wired-OR bus confi... | 06/13/2000 |
| 6076177 | Method and apparatus for testing a circuit module concurrently with a non-volatile memory operation in a multi-module data processing system Testing of a multi-module data processing system (20) includes performing a functional test on a module (42, 44, 46, 48, 50, 54) concurrently with an erase operation of a non-volatile memory module (34, 36). Because the erase operation requires multiple c... | 06/13/2000 |
| 6076178 | Test circuit and method for DC testing LSI capable of preventing simultaneous change of signals A test circuit for DC testing which has a simple layout design and never causes malfunction due to simultaneous change of outputs includes test circuits connected to inputs of output allowable buffers. The test circuits are connected in a circle so that a... | 06/13/2000 |
| 6076179 | Method and apparatus of increasing the vector rate of a digital test system The present invention provides a method and apparatus for increasing the vector rate of an integrated circuit test system and simplifying the wiring of the tester to the device under test. The tester incorporates circuitry that allows the CPU to remap ass... | 06/13/2000 |
| 6076180 | Method for testing a controller with random constraints A method for testing an IDE controller with random constraints, the method comprising: providing an IDE controller model having a primary and a secondary channel and a host interface; transmitting data patterns to a primary and a secondary device model; r... | 06/13/2000 |
| 6076181 | Method and apparatus for controlling a retransmission/abort timer in a telecommunications system A method and apparatus for controlling a retransmission/abort timer in a telecommunications system. A pointer, V(P), that points to the upper bound of retransmitted data frames in a receiver buffer is introduced. A list includes at least one entry indicat... | 06/13/2000 |
| 6076182 | Memory fault correction system and method A memory fault correction system enables plural data bit errors in a single data word to be corrected in an efficient manner. The system divides each data word into a plurality of sub-words and creates a separate error correction code for each of the sub-... | 06/13/2000 |
| 6076183 | Method of memory error correction by scrubbing The invention relates to a method of correction of corrupted data stored in a memory location by scrubbing. The memory is associated with an error correcting code device which corrects the data transmitted to a user requesting them. The method comprises t... | 06/13/2000 |
| 6076184 | Information recording method, reproducing method, and reproducing apparatus In a system recording compressed video and audio signals or computer user data on a disk in the sector unit, to reproduce the data in a simple fashion at a high speed, data to be recorded on the disk is divided into data in a predetermined unit so as to a... | 06/13/2000 |
