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| Number | Title | Issue Date |
| 6058489 | On-line disk array reconfiguration A system for performing on-line reconfiguration of a disk array in which a source logical volume is reconfigured to a destination logical volume. Disk array configuration is invoked if a new physical drive is inserted, or a drive is removed. Reconfigurati... | 05/02/2000 |
| 6058490 | Method and apparatus for providing scaleable levels of application availability A method and an apparatus for providing scalable layers of highly available applications using loosely coupled commercially available computers. The software running on the loosely coupled computers is divided into three layers: the system layer, the plat... | 05/02/2000 |
| 6058491 | Method and system for fault-handling to improve reliability of a data-processing system A method and system for handling detected faults in a processor to improve reliability of a computer system is disclosed. A fault-tolerant computer system is provided which includes a first processor, a second processor, and a comparator. Coupled to a sys... | 05/02/2000 |
| 6058492 | Method and apparatus for design verification using emulation and simulation A method and apparatus for combining emulation and simulation of a logic design. The method and apparatus can be used with a logic design that includes gate-level descriptions, behavioral representations, structural representations, or a combination there... | 05/02/2000 |
| 6058493 | Logging and reproduction of automated test operations for computing systems A system, method, and computer program product for performing an evaluation of a software product wherein a logging module stores in a storage area, such as log file, a description of each loggable test step performed by automated test software. When the ... | 05/02/2000 |
| 6058494 | Storage system with procedure for monitoring low level status codes, deriving high level status codes based thereon and taking appropriate remedial actions A controller of a storage system for computer data enables diagnosis of errors and status monitoring of the storage system. The controller is enabled to categorize errors according to severity and to analyze low-level errors so as to trigger a combination... | 05/02/2000 |
| 6058495 | Multi-bit test circuit in semiconductor memory device and method thereof A multi-bit test circuit detects the fail cells in a memory block accurately even though there exists a short bridge between bit lines or between memory cells. The circuit includes an input buffer for transferring a same test data bit received from a mult... | 05/02/2000 |
| 6058496 | Self-timed AC CIO wrap method and apparatus A method and apparatus for testing a semiconductor chip includes providing the semiconductor chip with a common input/output (I/O) or bidirectional I/O pad. The I/O pad is electrically coupled to an off-chip driver (OCD) and an off-chip receiver (OCR). Th... | 05/02/2000 |
| 6058497 | Testing and burn-in of IC chips using radio frequency transmission A testing system evaluates one or more integrated circuit chips using RF communication. The system includes an interrogator unit with a radio communication range, and an IC chip adapted with RF circuitry positioned remotely from the interrogator unit, but... | 05/02/2000 |
| 6058498 | Dot code and information recording/reproducing system for recording/reproducing the same A long time optical recording and repeated reproduction of multimedia information is possible. Using a printer system or printing process system, on a recording medium such as a sheet, the so-called multimedia information in the form of dot codes (36) tog... | 05/02/2000 |
| 6058499 | Error correcting method and device Reed-Solomon encoded data read from a CD-ROM, DVD-ROM, or other recording or transmission source is error corrected at high speed in an apparatus that employs a pair of byte-wide error correcting sub-circuits operating substantially in parallel. An MSB pl... | 05/02/2000 |
| 6058500 | High-speed syndrome calculation A method and device for calculating syndromes used in forward-error-correction codes. To calculate syndromes more quickly using a computer with memory access latency, the polynomial equation C(X) is divided by a generator polynomial G(X) to form a remaind... | 05/02/2000 |
| 6058501 | Error detecting device for viterbi decoder An error detecting device of received digital data solves a problem for detecting errors in a conventional device in that error detection following the Viterbi decoding performed on most important bits cannot detect errors even if they include a considera... | 05/02/2000 |
| 6058502 | Diagnostic system analyzing frequency spectrum of electric power for diagnosing integrated circuit, method and information storage medium storing computer program for the method A diagnosis system for a semiconductor integrated circuit repeatedly applies a test pattern at repetition periods so as to measure variation of electric power supplied to the semiconductor integrated circuit, and determines the magnitude of a spectral com... | 05/02/2000 |
