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| Number | Title | Issue Date |
| 6047362 | Delayed removal of address mapping for terminated processes An application binary interface includes linkage structures for interfacing a binary application program to a digital computer. Virtual address spaces are allocated for processes respectively. Page table entries for translation of the virtual address spac... | 04/04/2000 |
| 6047363 | Prefetching data using profile of cache misses from earlier code executions During execution of a code sequence, a profile is generated containing addresses of the data cache misses experienced during the execution. The profile is associated with the code sequence such that, during a future execution of the code sequence, the pro... | 04/04/2000 |
| 6047364 | True modulo addressing generator In accordance with the present invention, an address arithmetic unit provides a modulo addressing technique for addressing a circular buffer. The address arithmetic unit includes a first selector adapted to receive as a first input a value representative ... | 04/04/2000 |
| 6047365 | Multiple entry wavetable address cache to reduce accesses over a PCI bus A method and apparatus for optimizing sample fetching in a peripheral component interconnect (PCI) environment. In one embodiment the present invention generates a first sample page base address corresponding to a first part of a first address received fr... | 04/04/2000 |
| 6047366 | Single-instruction multiple-data processor with input and output registers having a sequential location skip function A single-instruction multiple-data (SIMD) processor (10) that incorporates features for horizontal scaling of video data. The processor (10) has a data input register (11) that is operable to store input data word in sequential locations in the data input... | 04/04/2000 |
| 6047367 | Microprocessor with improved out of order support A system and method for improving microprocessor computer system out of order support via register management with synchronization of multiple pipelines and providing for processing a sequential stream of instructions in a computer system having a first a... | 04/04/2000 |
| 6047368 | Processor architecture including grouping circuit A processor which includes separate instruction and data caches and which executes instructions according to a new instruction set architecture efficiently executes software code by providing the processor with a grouper circuit which receives software co... | 04/04/2000 |
| 6047369 | Flag renaming and flag masks within register alias table A mechanism and method for renaming flags within a register alias table ("RAT") to increase processor parallelism and also providing and using flag masks associated with individual instructions. In order to reduce the amount of data dependencies between i... | 04/04/2000 |
| 6047370 | Control of processor pipeline movement through replay queue and pointer backup The invention, in one embodiment, is a processor pipeline. The pipeline includes a front end, a back end, and a queue between the front end and the back end. The queue is capable of storing an intermediate state of the processor from which the back end ma... | 04/04/2000 |
| 6047371 | Signal processor for performing conditional operation To provide a signal processor for performing processing in fewer cycles by selecting one of the two different operations in accordance with a flag signal and performing the selected operation without the use of a conditional branch instruction, the signal... | 04/04/2000 |
| 6047372 | Apparatus for routing one operand to an arithmetic logic unit from a fixed register slot and another operand from any register slot A multimedia extension unit (MEU) is provided for performing various multimedia-type operations. The MEU can be coupled either through a coprocessor bus or a local CPU bus to a conventional processor. The MEU employs vector registers, a vector ALU, and an... | 04/04/2000 |
| 6047373 | Method and apparatus for setting the operating parameters of a computer system An apparatus includes a configuration selector that is selectively configurable to denote one of a plurality of operating modes for the apparatus, including a configuration mode. The apparatus further comprising a programmable multiplexer, a processor, a ... | 04/04/2000 |
| 6047374 | Method and apparatus for embedding authentication information within digital data Arbitrary digital information is embedded within a stream of digital data, in a way that avoids detection by a casual observer and that allows a user to determine whether the digital data have been modified from their intended form. The embedded informati... | 04/04/2000 |
| 6047375 | Cryptographic processor with interchangeable units A computer system having multiple processors wired to a common MCM substrate in which insertable processor chips themselves carry fencing appropriate to their function on the multi-chip module in which they are inserted for optimizing needed functions wit... | 04/04/2000 |
| 6047376 | Client-server system, server access authentication method, memory medium stores server-access authentication programs, and issuance device which issues the memory medium contents It is necessary to authenticate each access by permitting or refusing it when a client makes an access to a server in a client-server system in which clients and servers are interconnected via a network. The client utilizes memory medium which stores both... | 04/04/2000 |
| 6047377 | Typed, parameterized, and extensible access control permissions A method and apparatus for establishing and maintaining complex security rules is provided. The security rules are established through the use of "permission" classes that take advantage of the power and simplicity various features of object oriented prog... | 04/04/2000 |
| 6047378 | Wake multiple over LAN Multiple stations, such as Personal Computers, are awakened (restored to full power) by a specially formatted Local Area Network (LAN) frame termed "Wake Multiple Over LAN". The frame includes a header field containing Destination Addresses, DA, of statio... | 04/04/2000 |
| 6047379 | Information bus regenerator A bus regenerator, and an extended bus information system and method of communicating information, using such a regenerator. A bus regenerator has first and second information buses. A processor is connected to transfer information between the buses and a... | 04/04/2000 |
| 6047380 | Microcontroller wake-up function having an interleaving priority scheme for sampling a plurality of analog input signals A semiconductor device for receiving analog input signals includes a microprocessor for processing signal information. The microprocessor is put in a sleep mode when not called upon to process signal information, and is either left in that mode or awakene... | 04/04/2000 |
| 6047381 | Variable speed controller A variable speed controller is disclosed that is capable of processing selected commands at a faster-than-normal rate. The invention is useful in the context of x86-based microcomputers to speed up the execution of MASK-A20 and/or RESET-CPU commands that ... | 04/04/2000 |
| 6047382 | Processor with short set-up and hold times for bus signals A processor includes a system bus interface that permits short set-up and hold times for bus signals including loop-back signals. Loop-back signals are transferred from an input cell in the interface to a target I/O cell in the interface without resynchro... | 04/04/2000 |
| 6047383 | Multiple internal phase-locked loops for synchronization of chipset components and subsystems operating at different frequencies Methods and apparatus for easing design constraints with respect to placement of computer system components and subsystems requiring relative synchronicity at different frequencies is described. In one embodiment the apparatus includes a first phase-locke... | 04/04/2000 |
| 6047384 | Rapid recovery and start-up system for peripheral systems The start-up of a computer system takes place rapidly using a computer system having a recovery system which collects data for the recovery in parallel fashion in a common memory so that the data can be transferred to peripheral units of the computer syst... | 04/04/2000 |
| 6047385 | Digital cross-connect system restoration technique Full restoration of a telecommunications network element (12), such as a digital cross-connect system (DCS), is accomplished by receiving from each element provisioning updates as they occur in real time via a local controller network (18). The provisioni... | 04/04/2000 |
| 6047386 | Apparatus for scan test of SRAM for microprocessors having full scan capability An apparatus for allowing a RAM array within an SRAM to be tested via scan ATPG is disclosed. A first clocked flip-flop has a data input latched high, a scan-in input latched high, a clock input coupled to a signal source generating a periodic waveform, a... | 04/04/2000 |
| 6047387 | Simulation system for testing and displaying integrated circuit's data transmission function of peripheral device A system implement simulation system's capable of facilitating integrated circuit designers to perform a complete integrated circuit testing with respect to a target peripheral device and demonstrate various functions and their sequence of operations with... | 04/04/2000 |
| 6047388 | Method and apparatus for processing an invalid address request A method, apparatus, and computer program product are provided for processing an invalid address request in a computer system. A processor in the computer system receives an address requested from software and compares a real address requested with a real... | 04/04/2000 |
| 6047389 | Testing of a software application residing on a hardware component According to the system and method, at least one test script is provided for testing a function of the software application. A testing interface, loaded into the hardware component, is operable to input the test script into the software application. A dis... | 04/04/2000 |
| 6047390 | Multiple context software analysis A method for multiple context analysis of software applications in a multiprocessing (22, 23), multithreaded computer environment utilizes instrumentation code inserted (54, 55) into the applications. For each execution (67) of the application (60), a con... | 04/04/2000 |
| 6047391 | Method for strong partitioning of a multi-processor VME backplane bus A method for strong partitioning of multi-processor applications that maintains fault containment on the VMEbus is presented. The method implements a message passing mechanism to increase fault tolerance and localize and contain detected faults on any one... | 04/04/2000 |
| 6047392 | System and method for tracking dirty memory A system and method for tracking dirty memory which, in one embodiment, comprises a first memory corresponding to a first processor, a second memory corresponding to a second processor and a third memory coupled to the first memory, wherein the third memo... | 04/04/2000 |
| 6047393 | Memory testing apparatus There is provided a memory testing apparatus which can complete a DC test FOR a memory in a short time period. A pattern generator 2 comprises a hold time setting device 2A for setting a hold time during which a test signal of a predetermined pattern is k... | 04/04/2000 |
| 6047394 | Circuit for easily testing a logic circuit having a number of input-output pins by scan path A scan path circuit is for use in testing a logic package designed in accordance with scan path fashion. The logic package comprises a logic circuit and a plurality of scan paths. The logic circuit has first through N-th input/output pins, where N represe... | 04/04/2000 |
| 6047395 | Error correction processor for correcting a multi-dimensional code by generating an erasure polynomial over one dimension for correcting multiple codewords in another dimension An error correction processor is disclosed for correcting errors in binary data read from a disk storage medium, wherein the binary data comprises a first and second set of intersecting ECC codewords of a multi-dimensional codeword. The error correction p... | 04/04/2000 |
| 6047396 | Digital data storage system including phantom bit storage locations A digital data storage arrangement includes a storage register for storing a data word having a predetermined number of data bits along with an error correction code, a data input circuit and a data output circuit. The data input circuit receives an input... | 04/04/2000 |
| 6047397 | Read device for a record carrier A read device for reading a record carrier which has recorded thereon a data signal which represents data words, added codewords of a first type and added codewords of a second type. The added codewords of the first type have a predefined first relation t... | 04/04/2000 |
| 6047398 | Reproducing method, reproducing apparatus and recording and reproducing apparatus using the same reproducing method, and recording medium having the same method recorded therein A reproducing method for reproducing data from tracks recording signals interleaves over plural tracks, storing the reproduced data, processing the stored data by error correction, issuing an error correction disable signal in the case of data processing ... | 04/04/2000 |
