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| Number | Title | Issue Date |
| 5933849 | Scalable distributed caching system and method A scalable distributed caching system on a network receives a request for a data object from a user. The caching system carries out a locator function that locates a directory cache for the object. The directory cache stores a directory list that identifi... | 08/03/1999 |
| 5933850 | Instruction unit having a partitioned cache An instruction cache which separates storage cells for instruction data from storage cells for sequence control is disclosed. Instructions are decoded prior to being stored to the instruction cache which serves a primary cache, while prior hierarchical le... | 08/03/1999 |
| 5933851 | Time-stamp and hash-based file modification monitor with multi-user notification and method thereof An information management device includes a setter for setting an address of a file to be monitored, an accessor for accessing the address set by the setter at a prescribed timing, a determiner for determining updating of the file and a controller for con... | 08/03/1999 |
| 5933852 | System and method for accelerated remapping of defective memory locations A computer system includes a memory requester that interfaces with a memory module that includes memory portions. A remapping table that maps each of the defective memory portions to a respective non-defective memory portion in the memory module is create... | 08/03/1999 |
| 5933853 | Removable storage-medium assembled-type large-capacity information storage apparatus and information processing method Data is stored in a cache memory, a cache HDD, high frequently accessed optical discs, or low frequently accessed optical discs, and the data is transferred between the cache memory and the cache HDD under the control of a control device which predicts th... | 08/03/1999 |
| 5933854 | Data security system for transmitting and receiving data between a memory card and a computer using a public key cryptosystem In a system wherein a memory card is connected to a computer, data stored in a memory device in the memory card is read by a processor provided in the computer. An address signal and a data signal from the computer to the memory card, and/or a data signal... | 08/03/1999 |
| 5933855 | Shared, reconfigurable memory architectures for digital signal processing Architectures and circuits are described for various implementations of a memory-centric computing system for DSP and other compute-intensive applications. A shared, reconfigurable memory system is accessible to both a host processor or controller and to ... | 08/03/1999 |
| 5933856 | System and method for processing of memory data and communication system comprising such system The present invention relates to a system for processing of memory data in the form of stored variables. The system comprises at least one data execution unit (IPU), a common data memory (DS), a central processor bus and a function unit (30) for autonomou... | 08/03/1999 |
| 5933857 | Accessing multiple independent microkernels existing in a globally shared memory system Microkernel memory references, traditionally required to refer to memory by exact physical address, are transformed so as to be able to map the references to addresses in multiple memory nodes. As a result, each node's address space may be compiled to by ... | 08/03/1999 |
| 5933858 | Efficient internal address encoding scheme for an integrated circuit which facilitates multiple addressing modes An address line arrangement which uses weighted sets of mutually independent rather than binary address lines to enable the accessing of any number of targeted elements at one time. The elements in a device are divided into groups of elements. For a numer... | 08/03/1999 |
| 5933859 | Processor to memory interface logic for use in a computer system using a multiplexed memory address Interface logic for interfacing a processor to a memory unit is disclosed. The interface logic in one embodiment of the present invention uses a single port to both receive an address from the processor and drive a multiplexed address to the memory unit. ... | 08/03/1999 |
| 5933860 | Multiprobe instruction cache with instruction-based probe hint generation and training whereby the cache bank or way to be accessed next is predicted A computer system including an instruction cache (I-cache) having a plurality of banks for storing a subset of data from memory is shown to include a prediction mechanism for predicting which bank of the I-cache contains the required data. A prediction va... | 08/03/1999 |
| 5933861 | Parallel memory device for image processing utilizing linear transformation A parallel memory device for an image processing utilizing a linear transformation, capable of achieving simultaneous access in either of various access forms which uses simple hardware and is capable of achieving a high processing rate and thereby a high... | 08/03/1999 |
