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"That’s an amazing invention, but who would ever want to use one of them?"
President Rutherford B. Hayes ; Said in 1876, after Alexander Graham Bell demonstrated the telephone to him at the White House
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| Number | Title | Issue Date |
| 5860150 | Instruction pre-fetching of a cache line within a processor An apparatus for fetching data from a main memory into a primary cache memory of a processor. Instruction fetch requests are generated by the processor and assigned a priority level according to the predicted accuracy of the fetch request. The priority le... | 01/12/1999 |
| 5860151 | Data cache fast address calculation system and method The data cache features an improved mechanism for accessing data from the data memory array of a data cache, by generating a predicted address and using it to access the data cache array in parallel with the effective address computation. The logic circui... | 01/12/1999 |
| 5860152 | Method and apparatus for rapid computation of target addresses for relative control transfer instructions A method and apparatus accepts a relative control transfer instruction and generates a compact absolute control transfer instruction which may have a number of bits one greater than the relative control transfer instruction and including flags to rapidly ... | 01/12/1999 |
| 5860153 | Memory efficient directory coherency maintenance A bit map is maintained by a provider object of a name server to keep track of names cached by a cache object of the client. The bit map is indexed by performing a hash of the name. When a name is looked up by the server on behalf of a client, the server ... | 01/12/1999 |
| 5860154 | Method and apparatus for calculating effective memory addresses A macro instruction is provided for a microprocessor which allows a programmer to specify a base value, index, scale factor and displacement value for calculating an effective address and returning that result in a single clock cycle. The macro instructio... | 01/12/1999 |
| 5860155 | Instruction decoding mechanism for reducing execution time by earlier detection and replacement of indirect addresses with direct addresses The mechanism includes a virtual address detecting circuit for detecting the virtual address of the instruction code. When a virtual address is detected, an indicating signal is generated, which is then sent to an indirect address register to register the... | 01/12/1999 |
| 5860156 | Method for implementing an indexed jump table A method for processing interface messages, such as SCSI messages, using an indexed jump table. Two single-dimensional tables are implemented by the method described. The first table stores index values for all valid sequence instruction locations for whi... | 01/12/1999 |
| 5860157 | Nonvolatile memory card controller with an optimized memory address mapping window scheme A method of locating a memory address of a nonvolatile memory card that corresponds to an external address in an integrated circuit card controller that controls memory operation of the card is described. The controller includes a first memory address map... | 01/12/1999 |
| 5860158 | Cache control unit with a cache request transaction-oriented protocol A cache control unit and a method of controlling a cache. The cache is coupled to a cache accessing device. A first cache request is received from the device. A request identification information is assigned to the first cache request and provided to the ... | 01/12/1999 |
| 5860159 | Multiprocessing system including an apparatus for optimizing spin--lock operations A multiprocessing system having a plurality of processing nodes interconnected by an interconnect network. To optimize performance during spin-lock operations, a home agent prioritizes the servicing of read-to-own (RTO) transaction requests over the servi... | 01/12/1999 |
| 5860160 | High speed FIFO mark and retransmit scheme using latches and precharge The present invention provides a look ahead architecture to satisfy the retransmit recovery time constraints in a mark and retransmit system while allowing a full bitline precharge. A number of sense amplifiers are provided in the look ahead architecture ... | 01/12/1999 |
| 5860161 | Microcontroller configured to indicate internal memory accesses externally A microcontroller integrates a memory accessible by the processor core. Additionally, the microcontroller provides an indication upon an external bus that memory accesses mapped to the integrated memory are occurring, independent of the enablement status ... | 01/12/1999 |
