Bizarre Patents
Dining Table Having Integral Dishwasher
A space-saving dishwasher, which may be installed within a counter top or table, having a dish-carrying rack that is vertically shiftable through the open top of the dishwasher for facilitating loading and unloading of the dishes.
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| Number | Title | Issue Date |
| 5636359 | Performance enhancement system and method for a hierarchical data cache using a RAID parity scheme A system and method for reducing device wait time in response to a host initiated write operation modifying a data block. The system includes a host computer channel connected to a storage controller which has cache memory and a nonvolatile storage buffer... | 06/03/1997 |
| 5636360 | Method for preventing overwriting cache buffer transaction entries until corresponding log buffer entries have been copied to log partition of the disk A method for logging transactions which alters a file system stored on a secondary storage device is disclosed. The method includes the steps of writing data to a buffer in a buffer cache and logging the transaction in a log buffer residing on a primary s... | 06/03/1997 |
| 5636361 | Multi-processor computer system having dual memory subsytems for enabling concurrent memory access thereto by more than one processor A multi-processor information handling system employs multiple multi-processor bus/memory subsystem groups wherein the processors may operate programs concurrently, and concurrent memory operations may be performed with the multiple memory subsystems via ... | 06/03/1997 |
| 5636362 | Programmable high watermark in stack frame cache using second region as a storage if first region is full and an event having a predetermined minimum priority A programmable high watermark for a stack frame cache for eliminating frame spills initiated by certain critical events. A stack frame cache in a microprocessor is divided into two regions. The second region in the stack frame cache is reserved for contex... | 06/03/1997 |
| 5636363 | Hardware control structure and method for off-chip monitoring entries of an on-chip cache A structure and a method for directing execution of instructions are provided in a microprocessor with an on-chip cache memory. In one embodiment, the microprocessor provides a debug mode, which is activated by a signal on a mode pin. In the debug mode, w... | 06/03/1997 |
| 5636364 | Method for enabling concurrent misses in a cache memory In a cache-to-memory interface, a means and method for timesharing a single bus to allow the concurrent processing of multiple misses. The multiplicity of misses can arise from a single processor if that processor has a nonblocking cache and/or does specu... | 06/03/1997 |
| 5636365 | Hierarchical buffer memories for selectively controlling data coherence including coherence control request means A buffer-memory coherence control mechanism for a data processing system includes a coherence control identification device. For each entry of a second buffer memory to which a plurality of first buffer memories is connected, a control bit for coherence c... | 06/03/1997 |
| 5636366 | System and method for preserving instruction state-atomicity for translated program A system or method is provided for translating a first program code to a second program code and for executing the second program code while preserving instruction state-atomicity of the first code. The first program code is executable on a computer havin... | 06/03/1997 |
| 5636367 | N+0.5 wait state programmable DRAM controller CPU system performance is improved by reducing the time required to complete a DRAM access by microprocessors such as the 386DX, 386SX and 80286 by incorporating a programmable DRAM controller therewith which permits consecutive DRAM accesses to average N... | 06/03/1997 |
| 5636368 | Method for programming complex PLD having more than one function block type A method for programming programmable logic devices (PLDs) having multiple function block types to implement a logic function, whereby the logic function is mapped into one of the function block types before being mapped into the remaining function block ... | 06/03/1997 |
| 5636369 | Fast pattern-detection machine and method The invention is a state machine for the detection of a pre-specified pattern of m bits in a stream of bits where the stream of bits is examined in steps, each successive step consisting of the examination of the next successive set of n bits in the strea... | 06/03/1997 |
| 5636370 | System and method for interfacing risc busses to peripheral circuits using another template of busses in a data communication adapter A conversion cache circuit, interfacing RISC busses to CISC peripheral circuits, provides master/slave Write and Read operations in a shared memory (130) and in the internal registers of the processor of said peripheral circuits (210). It enables RISC pro... | 06/03/1997 |
| 5636371 | Virtual network mechanism to access well known port application programs running on a single host system A local host data processing system operating under the control of a local host operating system includes components of a hosted operating system. The host operating system further include a TCP/IP network protocol stack which couples to the communication... | 06/03/1997 |
| 5636372 | Network timing analysis method which eliminates timing variations between signals traversing a common circuit path A method of analyzing timing differences between arrival times of distinct signals propagating through a circuit comprising: (i) identifying a first beginning point for a first data path over which data arrival times are propagated to a data endpoint; (ii... | 06/03/1997 |
| 5636373 | System for synchronizing logical clock in logical partition of host processor with external time source by combining clock adjustment value with specific value of partition An external time source is connected to a partitioned data processing system, having host processors controlled by a host hypervisor, and having operating systems in the partitions. The host processors each have a timer facility comprising a time-of-day (... | 06/03/1997 |
| 5636374 | Method and apparatus for performing operations based upon the addresses of microinstructions In a microprocessor, an apparatus and method for performing memory functions and issuing bus cycles. Special microinstructions are stored in microcode ROM. These microinstructions are used to perform the memory functions and to generate the special bus cy... | 06/03/1997 |
| 5636375 | Emulator for high speed, continuous and discontinuous instruction fetches A jump judgment circuit judges whether an instruction read bus cycle of a CPU to be emulated is to be executed in a sequential order of addresses of a memory. A control circuit operates in accordance with the judgment result. Specifically, if an instructi... | 06/03/1997 |
| 5636376 | System and method for selectively and contemporaneously monitoring processes in a multiprocessing server A system, method and program product for determining and displaying the status of client application programs executing on a multiprocessing server. Server process control blocks and synchronization object descriptors are created in the shared memory of t... | 06/03/1997 |
