Did You Know...
...that the video game, Pong, was invented by a guy who graduated at the bottom of his engineering class? Nolan Bushnell spent more time running the games at a local amusement park than he did on his studies at the University of Utah. His dreams of working for Disney's amusement empire were dashed when the company wouldn't hire him. Taking a boring job, Nolan daydreamed about electronic versions of popular games. He invented Pong, the first video game, and went on to found Atari Co.
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| Number | Title | Issue Date |
| 5502805 | System and methods for improved spreadsheet interface with user-familiar objects An electronic spreadsheet system of the present invention includes a notebook interface having a plurality of notebook pages, each of which may contain a spread of information cells, or other desired page type (e.g., Graphs page). Methods are provided for... | 03/26/1996 |
| 5502806 | Waiting line management system A waiting line management system that can be applied in any setting where usage demand exceeds the capacity for any attraction (ride, event, concert, food service outlet or any other type of entertainment, product or service) which results in a waiting pe... | 03/26/1996 |
| 5502807 | Configurable video sequence viewing and recording system A configurable video sequence viewing and recording system stores multiple computer generated images of a sequence in a frame buffer and plays back the images for animation motion study. The images are stored either in a full size format or in a decimated... | 03/26/1996 |
| 5502808 | Video graphics display system with adapter for display management based upon plural memory sources Video graphics display system having a display adapter connected between a host processor (2) and a display unit (6). The display adapter includes a video memory (4) which has first and second memory parts (3) and (8). A graphics processor (1) is connecte... | 03/26/1996 |
| 5502809 | Image storage of a changeable display A VRAM for storing saved images are provided for quick transfer of images to a VRAM for storing displayed images. An image controller controls transfer of images among VRAM for storing displayed images, VRAM for storing saved images, and RAM for storing s... | 03/26/1996 |
| 5502810 | Optical transmission system An optical transmission system of the present invention has a tributary station and a plurality of repeater stations. The tributary station supplies a transmission signal having a data signal and a control signal. Each of the repeater stations detects the... | 03/26/1996 |
| 5502811 | System and method for striping data to magnetic tape units A plurality of removable volumes for magnetic tape units are used as array for the storage of data. First an array of removable volumes is mounted on the magnetic tape units. Then each removable volume of the array is accessed at equivalent logical locati... | 03/26/1996 |
| 5502812 | Method and system for automatic fault detection and recovery in a data processing system In the event of failure of a processor module (PMI) which is part of a data processing system the processor module (III.1) is turned off and then on; preferably, complete reconfiguration (III.2) of the module is commanded only if at least one other fault,... | 03/26/1996 |
| 5502813 | Method and apparatus for testing an NVM Apparatus for testing an NVM comprising, a microprocessor, a plurality of NVMs respectively connected to the microprocessor, each of the NVMs having an address space for storing data therein, and the microprocessor including, structure for selecting one o... | 03/26/1996 |
| 5502814 | Method of detecting defective memory locations in computer system A method of detecting defective memory locations by determining a slot number corresponding to a memory address, when read data disagree with written data, determining a memory size corresponding to the determined slot number, determining relationships be... | 03/26/1996 |
| 5502815 | Method and apparatus for increasing the speed at which computer viruses are detected The method and apparatus for increasing the speed at which computer viruses are detected stores initial state information concerning the file or volume which is being examined for a virus. This information is stored in a cache in a non-volatile storage me... | 03/26/1996 |
| 5502816 | Method of routing a request for a virtual circuit based on information from concurrent requests A method of routing a requested virtual circuit in a network advantageously uses information about concurrent requests for other virtual circuits. Each virtual circuit request in a set of concurrent requests is specified by one or more parameters and each... | 03/26/1996 |
| 5502817 | Ultra high speed data collection, processing and distribution ring with parallel data paths between nodes A high speed data collection processing and distribution system for coupling a plurality of digital data sources to a plurality of digital data processors. The system includes a plurality of segmented parallel data paths and a plurality of nodes connectin... | 03/26/1996 |
| 5502818 | Procedure for the determination of message identification in the data transmission network of an elevator system A procedure is disclosed for determining the message identifiers in a control area network CAN data transmission network of an elevator system where message identifiers are used in the transmission of messages. Each node in the network monitors the data t... | 03/26/1996 |
| 5502819 | Clock distribution system for reducing clock skew between processors in a dual sided tightly coupled system A clock distribution system for reducing clock skew between tightly coupled central processing units in a multi-processor system. The multi-processor system includes (1) a configuration processor for generating a first configuration signal and a second co... | 03/26/1996 |
| 5502820 | Microprocessor having high speed, low noise output buffers An improved buffer circuit arrangement is provided which is particularly useful for semiconductor integrated circuit semiconductor memories and microprocessors. The buffer circuit is capable of switching large loads in various types of LSIs, and features ... | 03/26/1996 |
| 5502821 | Method of determining devices requesting the transfer of data signals on a bus A method is described for determining readiness of devices in a digital data bus system to transfer data signals. The bus system includes a bus having a clock line for communicating a clock signal, address lines for communicating address signals, data lin... | 03/26/1996 |
| 5502822 | Asynchronous data transmission system An asynchronous data transmission system for asynchronously transmitting data from a first system controller to a second system controller in which a memory for holding therein data to be transmitted has a duplex structure including first and second memor... | 03/26/1996 |
| 5502823 | Bus system with virtual logical buffer A bus system is disclosed in which the CPU reads program controlling data from a ROM and stores the read data into a RAM through an internal bus line. The CPU causes interrupts on the RAM at predetermined timing to thereby supply data required for control... | 03/26/1996 |
| 5502824 | Peripheral component interconnect "always on" protocol A Peripheral Component Interconnect (PCI) bus has a protocol that guarantees that at all times, except for turn-around clocks necessary to prevent contention, that the bus is actively driven to a logic 1 or 0 by some device attached thereto. As long as al... | 03/26/1996 |
| 5502825 | Data processing system with an enhanced cache memory control A detect circuit is provided in a system such as an I/O mapped microcomputer system in order to detect whether or not an access address for a read access request generated by a central processing unit (CPU) is for a part (such as a status register in the ... | 03/26/1996 |
| 5502826 | System and method for obtaining parallel existing instructions in a particular data processing configuration by compounding instructions Scalable compound instruction set machine and method which provides for processing a set of instructions or program to be executed by a computer to determine statically which instructions may be combined into compound instructions which are executed in pa... | 03/26/1996 |
| 5502827 | Pipelined data processor for floating point and integer operation with exception handling A data processor which is capable of executing two kinds of instructions, such as an integer operation instruction and a floating-point operation instruction, and which has bits in a PSW to control the timing of accepting an exception (FPU exception) gene... | 03/26/1996 |
| 5502828 | Reducing memory access in a multi-cache multiprocessing environment with each cache mapped into different areas of main memory to avoid contention A cache control circuit reduces accesses of main memory in a multiple cache multiprocessing system. The circuit allows the use of multiple caches with a single central processing unit, and facilitates burst-mode operations.... | 03/26/1996 |
| 5502829 | Apparatus for obtaining data from a translation memory based on carry signal from adder An adder adds a displacement address to a base address to generate a virtual address. The adder includes carry indicating circuitry for generating a carry indicating signal indicating whether the addition of the displacement address to the base address re... | 03/26/1996 |
| 5502830 | Camera with memory address designation feature A memory device having a plurality of regions is provided with a designating circuit for performing data erasing and writing in a given memory region. A change circuit changes the memory region either after a predetermined number of erasing/writing cycles... | 03/26/1996 |
| 5502831 | Method for detecting unauthorized modification of a communication or broadcast unit A database unit monitors the communications occurring within at least one communication system for hardware identification codes of communication or broadcast units. Upon detecting the hardware identification code, the database unit compares the one recei... | 03/26/1996 |
| 5502832 | Associative memory architecture An association memory which permits the execution of all kinds of comparative operations. The associative memory includes a memory map (1) in which a search argument, which has been processed in a scanning module (3) and a masking unit (5,7), is compared ... | 03/26/1996 |
| 5502833 | System and method for management of a predictive split cache for supporting FIFO queues A first-in, first-out queue is implemented on two memory elements by enqueuing and dequeuing items from a first memory element and by swapping middle portions of the queue between the first memory element and the second memory whenever the first memory el... | 03/26/1996 |
| 5502834 | Memory interface apparatus for carrying out complex operation processing A memory interface apparatus includes: a pipeline register holding a data packet from a transmission path to provide an instruction code, a generation number, and data separately; a memory access unit accessing an image memory according to the instruction... | 03/26/1996 |
| 5502835 | Method for synchronously accessing memory An integrated circuit microprocessor (30) reads data from an external memory device (22, 23) through early overlapping memory access cycles, thus allowing efficient accesses to slower-speed memory. The microprocessor (30) drives a first address and activa... | 03/26/1996 |
| 5502836 | Method for disk restriping during system operation A method for restriping a striped disk array in a computer system without requiring the removal of the system from normal operation provides an efficient method to expand the disk array and incorporate the new storage into the striping scheme. When the op... | 03/26/1996 |
| 5502837 | Method and apparatus for clocking variable pixel frequencies and pixel depths in a memory display interface A method and apparatus for synchronizing pixel data flow within a memory display interface (MDI) to enable variable pixel depths, and to support display devices requiring differing pixel rates. A clock circuit receives a pixel clock from a DAC, and genera... | 03/26/1996 |
| 5502838 | Temperature management for integrated circuits A system for controlling temperature buildup in an IC employs a temperature sensor to provide an indication of the IC temperature to a control circuit which is configured to provide an operational clock rate to the IC which is less than the system clock r... | 03/26/1996 |
| 5502839 | Object-oriented software architecture supporting input/output device independence An object-oriented software architecture interacts with "real" input/output devices exclusively through "virtual" input/output devices. Since all human interface with the operating system is performed through such virtual devices, the system can accept an... | 03/26/1996 |
| 5502840 | Method and apparatus for advising a requesting process of a contention scheme to employ to access a shared resource A method and apparatus in a multiprocessor computer system which advises a requesting process of how it should wait for a system process having shared data and/or shared resources that is currently occupied by another process. The method begins by storing... | 03/26/1996 |
