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| Number | Title | Issue Date |
| 5490255 | Expedited execution of pipelined command having self-ordering operand processing requirements A pipelined computer which process operand data through a sequence of D,A,T,B,X and W stages includes a sidetrack queue. Data which exits the B stage prematurely, before the X stage is ready to immediately process such data, is held over in the sidetrack ... | 02/06/1996 |
| 5490256 | Method and mechanism for calling 32-bit functions from 16-bit functions In the field of mixed 16-bit and 32-bit code, a method and mechanism are provided to implement alterations in the dynamic portion of memory containing the data objects used by code in the 16-bit environment so that such data is accessible to code from the... | 02/06/1996 |
| 5490257 | RAM based FIFO memory half-full detection apparatus and method A method for detecting a half-full condition of a first-in, first-out memory array. The method of the invention includes the steps of a) moving a write pointer through the array to write data to alternating rows of the memory array; b) moving a read point... | 02/06/1996 |
| 5490258 | Associative memory for very large key spaces To provide for fast access times with very large key fields, an associative memory utilizes a location addressable memory and look up tables to generate from a key an address in memory storing an associated record. The look up tables, stored in a memory, ... | 02/06/1996 |
| 5490259 | Logical-to-real address translation based on selective use of first and second TLBs Under such a condition between outputs of AND circuits for outputting All "0" when one of zero detecting circuits of two register identifiers within an instruction register detects "0", instead of a content of a general-purpose register designated by thes... | 02/06/1996 |
| 5490260 | Solid-state RAM data storage for virtual memory computer using fixed-sized swap pages with selective compressed/uncompressed data store according to each data size A computer using virtual memory management employs a random-access type storage device such as a semiconductor memory for page swapping. The semiconductor memory is formatted to provide multiple partitions of varying block size, e.g., two block sizes, for... | 02/06/1996 |
| 5490261 | Interlock for controlling processor ownership of pipelined data for a store in cache Insures data integrity in process ownership indications by providing an ownership interlock on the data units in a pipeline to a store-in type of cache. An ownership interlock prevents any processor ownership change to occur (i.e. exclusive or readonly ow... | 02/06/1996 |
| 5490262 | Dual cache memory device with cache monitoring A CPU connected to a memory storing module programs has an instruction cache for reading a module header heading a module program and module instructions following the module header out of the memory, and storing and transferring them. An operand cache re... | 02/06/1996 |
| 5490263 | Multiported buffer memory system for disk drive complex A multiported buffer memory system provides access to four external sources which can access data words in any one of four memory modules. The functions of Reading and Writing and status information can occur simultaneously during the course of system cyc... | 02/06/1996 |
| 5490264 | Generally-diagonal mapping of address space for row/column organizer memories A method for storing data in a generally-diagonal pattern in blocks of a flash EEPROM array by which the least number of memory cells are affected by a failure of either a row conductor or a column conductor, and apparatus for addressing the flash array t... | 02/06/1996 |
| 5490265 | Late cancel method and apparatus for a high performance microprocessor system A late cancel method and apparatus for a high performance microprocessor system is disclosed. The invention is advantageously utilized in a microprocessor system comprising a processor, an external cache memory and a main memory. The processor incorporate... | 02/06/1996 |
| 5490266 | Process oriented logic simulation having stability checking A logic simulator for optimal configurability of combinatorial and sequential logic circuits in a simulated behavioral form. The present invention contains process oriented functional blocks with event posting to eliminate unnecessary evaluations in logic... | 02/06/1996 |
| 5490267 | Method for distinguishing between a 386-type central processing unit and A 286-type central processing unit A method is disclosed for distinguishing between the Intel 80386 and 80286 CPUs. Bits 12, 13, and 14 of the 386 flags word in the real mode are always zero in the 286 architecture and cannot be set, but can be set to a one on the 386. The method includes ... | 02/06/1996 |
| 5490268 | Method for changing an arrangement of an initial combinational circuit to satisfy prescribed delay time by computing permissible functions of output gates and remaining gates A method of automatically forming a combinational LSI circuit comprising two processes. A first process of computing the permissible function of each element (gate) of a given circuit. A second process of connecting a gate having a shorter signal propagat... | 02/06/1996 |
| 5490269 | Radix sorting method and means for minimizing movement of elements having common prefixes A computer implemented method for speeding up the recursive most significant digit radix sorting of a set of record keys in which the keys are scanned for a shared or common prefix, coded according to the point in the key where they differ and the value o... | 02/06/1996 |
| 5490270 | Simultaneous updates to the modification time attribute of a shared file in a cluster having a server and client nodes A system and method for avoiding serialization on updating the modification time of files in a cluster system. In accordance with the method, the modification time field of a file can be accessed by multiple readers or multiple writers and each client in ... | 02/06/1996 |
| 5490271 | Remote interrupt processing over a network A local application connected to a remote application over a computer network can interrupt processing of the remote application. To do so, a new communications link is opened, and an identifier of the remote process to be interrupted is passed to the rem... | 02/06/1996 |
| 5490272 | Method and apparatus for creating multithreaded time slices in a multitasking operating system A method and apparatus for subdividing a thread's processing cycles among a set of threadlets or regions within a thread or process. This is achieved through instructions in the application code which are interpreted by the operating system. The beginning... | 02/06/1996 |
| 5490273 | System of dedicated elementary data processing machines organized in multiple levels and selectively activated to process incoming events A data processing machine comprises a plurality of elementary machines (SUPMS, DEP, ARR, . . . ) disposed in a plurality of levels (level 1, level 2, . . .), and an event presentation device (PTA) responding to the arrival of an event by identifying the l... | 02/06/1996 |
| 5490274 | Modified buddy system for managing disk space A modified buddy system is adopted for managing disk space in a disk storage. The modified buddy system uses a minimal amount of memory space and provides very quick access to extents within the disk space. The modified buddy system utilizes a tree struct... | 02/06/1996 |
| 5490275 | Virtual radio interface and radio operating system for a communication device A communication device (100) includes three levels and at least one feature and at least one protocol for communicating with other communication devices. The three levels are high level or user ergonomics (302), common level or feature/protocol (310), and... | 02/06/1996 |
| 5490276 | Programming language structures for use in a network for communicating, sensing and controlling information An improved programming interface which provides for event scheduling, improved variable declarations allowing for configuration of declaration parameters, and improved handling of I/O objects. In modern day computing devices and especially in networks of... | 02/06/1996 |
| 5490277 | Digital computation integrated circuit A digital computation integrated circuit has instruction memory for storing an instruction data, a store address designating part for designating a storing address of the instruction data in the instruction memory and for outputting the instruction data; ... | 02/06/1996 |
| 5490278 | Data processing method and apparatus employing parallel processing for solving systems of linear equations A linear calculating equipment comprises a memory for storing a coefficient matrix, a known vector and an unknown vector of a given system of linear equations, a pivoting device for choosing pivots of the matrix, a plurality of preprocessors for executing... | 02/06/1996 |
| 5490279 | Method and apparatus for operating a single CPU computer system as a multiprocessor system A method and apparatus for upgrading a uniprocessor system to a multiprocessing system simply by the insertion of a second microprocessor integrated circuit. The computer system is provided with an upgrade socket for receiving the second processing unit, ... | 02/06/1996 |
| 5490280 | Apparatus and method for entry allocation for a resource buffer A method and apparatus for allocating a number of vacant entries of a buffer resource and generating a set of enable vectors based thereon for a set of issued instructions. A deallocation vector of a reservation station is searched in order to locate, wit... | 02/06/1996 |
| 5490282 | Interface having serializer including oscillator operating at first frequency and deserializer including oscillator operating at second frequency equals half first frequency for minimizing frequency interference A serial communication interface for sending and receiving serial data is provided including a serializer and a deserializer. The serializer is designed so that the serializer VCO has a center frequency that is one half the center frequency of the deserializer... | 02/06/1996 |
| 5490283 | Adapter with FIFO and buffers for interfacing a handheld scanner to the parallel printer port of a portable computer An adapter system is used to interface a handheld scanner to the parallel printer port of a portable computer and includes a data buffer to receive serial video data from the handheld scanner and to convert the serial video data into parallel video data. ... | 02/06/1996 |
| 5490284 | Satellite/land mobile communication system integration scheme Through utilization of a transportable earth station capable of communicating with both of a mobile satellite communication system and a terrestrial based mobile communication system and a portable terminal which is capable of radio communication with the... | 02/06/1996 |
| 5490285 | Method of topographically displaying selected information in a cellular communication system A method is provided of topographically displaying selected information of a plurality of cells within a cellular communication system through a display device. The method includes the steps of accessing the selected information from an information databa... | 02/06/1996 |
| 5490286 | Synchronization of receiver to transmitter A location monitoring system is provided having a radio frequency transmitter for a person or object and radio frequency receiver for someone to monitor movement of the person or object, the receiver sounding an alarm at a predetermined time after failure... | 02/06/1996 |
| 5490287 | Wireless communication device and printing system using the same In a network of wireless communication devices, each device has a unit for transmitting information, a unit for variably controlling the transmission power for transmission of information, a unit for receiving information transmitted, and a unit for contr... | 02/06/1996 |
| 5490288 | Method for determining low signal quality communications In a communication system 100, failures can be determined without field testing in the following manner. For each transmission, a communication unit 104 determines the signal quality of the transmission. When the signal quality of the transmission is unfa... | 02/06/1996 |
