Bizarre Patents
Cloaking System Using Optoelectronically Controlled Camouflage
A Cloaking System designed to operate in the visible light spectrum, utilizes optoelectronics and/or photonic components to conceal an object within it.
PatentStorm News
Make the Most of Our Site
See this month's Top Inventors and Most Cited Patents.
Stay on top of the latest innovations by subscribing to an RSS feed.
Registered users: Manage your profile.
| Number | Title | Issue Date |
| 5469539 | Method for abstracting/detailing structuring elements of system specification information The specification abstracting-detailing system stores system specification information in a hierarchical structure. A hierarchy operation selects an object to be detailed or abstracted from the specification information, for updating hierarchical informat... | 11/21/1995 |
| 5469540 | Method and apparatus for generating and displaying multiple simultaneously-active windows The display system includes at least one central processing unit (CPU) which is coupled through appropriate input/output (I/O) circuitry to input devices, such as a keyboard, digital pad, mouse and/or trackball. The CPU is coupled to a hard disk drive for... | 11/21/1995 |
| 5469541 | Window specific control of overlay planes in a graphics display system Apparatus and methods for selectively controlling by graphics environment window the characteristics of an overlay common to multiple-windows while operating within the context of a conventional RAMDAC overlay control architecture. Window specific overlay... | 11/21/1995 |
| 5469542 | Serial diagnostic interface bus for multiprocessor systems Apparatus and method for use in a multiprocessor system (10) having a plurality of processing nodes (P0-P3) each of which includes a local data processor (22a, 28a). The apparatus includes an interface (42) to a controller (14), the interface including a ... | 11/21/1995 |
| 5469543 | Policing circuits arranged in matrix array for selectively transferring virtual path identifier (VPI) responsive to either VPI or service class identifier (SCI) threshold value In a policing arrangement for an ATM network, every incoming cell is stored in a cell buffer and a virtual path identifier (VPI) contained in the cell is extracted and translated to a corresponding one of a set of threshold values. Policing circuits of a ... | 11/21/1995 |
| 5469544 | Central processing unit address pipelining A microprocessor for use in a computer system which pipelines addresses for both burst and non-burst mode data transfers. By pipelining addresses, the microprocessor is able to increase the throughput of data transfers in the system. In the present invent... | 11/21/1995 |
| 5469545 | Expandable communication system with data flow control A communication system including one or more host adapters connected to a host computer, each adapter having multiple serial communication ports for transferring data between the computer and several TTY devices. Several of the adapter's serial ports incl... | 11/21/1995 |
| 5469546 | Method for retrying recording information into a next logical block by sending sense data including address information to host computer and responding to command therefrom A method of recording information on a recording medium which is incapable of erasing and overwriting. The method uses an information processing system comprising an information recording apparatus to record and verify information to the recording medium.... | 11/21/1995 |
| 5469547 | Asynchronous bus interface for generating individual handshake signal for each data transfer based on associated propagation delay within a transaction A method and apparatus is provided for use in an asynchronous bus interface capable of multiple or single width transfers and controlled by handshake signals, in which the bus transaction may include multiple successive data transfers delineated by a data... | 11/21/1995 |
| 5469548 | Disk array controller having internal protocol for sending address/transfer count information during first/second load cycles and transferring data after receiving an acknowldgement A disk array controller board which utilizes an EISA bus master which is a slave on its internal data bus to allow an advanced drive array controller chip (ADAC) to operate as a master. The ADAC is connected to transfer buffer RAM. The protocol of the int... | 11/21/1995 |
| 5469549 | Computer system having multiple asynchronous processors interconnected by shared memories and providing fully asynchronous communication therebetween A multi-processing computer system has multiple computing units. Each of the computing units includes a processor linked to a private memory via a private data bus, and each computing unit is linked to every other computing unit by a respective separate i... | 11/21/1995 |
| 5469550 | Reversible computer apparatus and methods of constructing and utilizing same A computer apparatus having a unique architecture which is capable of both forward and reverse execution modes. The reverse execution mode is implemented at the machine language level, and relies on an internal stack in micromemory or the microprocessor's... | 11/21/1995 |
| 5469551 | Method and apparatus for eliminating branches using conditional move instructions A high-performance CPU of the RISC (reduced instruction set) type employs a standardized, fixed instruction size, and permits only simplified memory access data width and addressing modes. The instruction set is limited to register-to-register operations ... | 11/21/1995 |
| 5469552 | Pipelined data processor having combined operand fetch and execution stage to reduce number of pipeline stages and penalty associated with branch instructions A data processing apparatus having a pipelined architecture, includes an instruction fetch unit for fetching an instruction from a memory; an instruction decode unit for decoding the instruction fetched by the instruction fetch unit, and outputting fetch ... | 11/21/1995 |
| 5469553 | Event driven power reducing software state machine For a computer system or a subsystem thereof having electrical components, a method and apparatus for a collection of event driven software state machine of the type where each state machine is separately operable at differing levels of power consumption,... | 11/21/1995 |
| 5469554 | Detecting the presence of a device on a computer system bus by altering the bus termination A computer system determines the presence of a device on the system bus that responds to I/O or memory reads by performing an I/O or memory read with data bus pulled to its normally undriven state. If the value returned is other than the data bus' normall... | 11/21/1995 |
| 5469555 | Adaptive write-back method and apparatus wherein the cache system operates in a combination of write-back and write-through modes for a cache-based microprocessor system Method and apparatus for reducing the access time required to write to memory and read from memory in a computer system having a cache-based memory. A dynamic determination is made on a cycle by cycle basis of whether data should be written to the cache w... | 11/21/1995 |
| 5469556 | Resource access security system for controlling access to resources of a data processing system A resource access security system for use in a data processing system for controlling access to resources correspondingly assigned to addresses in an address space of the data processing system by the use of descriptors. The descriptors correspondingly id... | 11/21/1995 |
| 5469557 | Code protection in microcontroller with EEPROM fuses A semiconductor microcontroller device is adapted to control the operation of an external system. The device includes a CPU, program memory for storing instructions to be executed by the CPU to perform its control functions, and data memory for storing da... | 11/21/1995 |
| 5469558 | Dynamically reconfigurable memory system with programmable controller and FIFO buffered data channels A memory system includes a main memory and a memory controller. The main memory includes at least one block which has a plurality of banks. The memory controller includes a plurality of data channels each of which can access at least one bank in the main ... | 11/21/1995 |
| 5469559 | Method and apparatus for refreshing a selected portion of a dynamic random access memory A system for refreshing selected portions of a dynamic access memory (DRAM) subsystem of a computer. A memory controller of the present invention includes a RAM device for storing a plurality of region descriptors used to inhibit the refresh of address ra... | 11/21/1995 |
| 5469560 | Prioritizing pending read requests in an automated storage library The average time a user must wait to have an object retrieved from an automated optical disk library is reduced by a method for prioritizing read requests. When a read request is received it is added to a queue of pending requests. All pending requests as... | 11/21/1995 |
| 5469561 | Apparatus and method for controlling the running of a data processing apparatus An apparatus and method for controlling the bus cycle running time of a data processing apparatus. The apparatus includes a CPU and at least one device such as a memory device, input/output device and the like which receives data from the C. A clock signa... | 11/21/1995 |
| 5469562 | Durable atomic storage update manager According to a first aspect of the invention, a DASUM (Durable Atomic Storage Update Manager) provides an extensible framework assuring complex changes to persistent storage of data within a computer system, including a distributed computer system. During... | 11/21/1995 |
| 5469563 | Method and control apparatus for self diagnosis A self diagnosis method and control apparatus for positive self diagnosis of equipment having complicatedly interlaced mechanical portions. Equipment under diagnosis is divided into a plurality of areas under diagnosis, each of which is assigned an evalua... | 11/21/1995 |
| 5469564 | Data storage device with enhanced data security A data storage device having the capability of preventing unauthorized access to data stored therein, including a memory, e.g., a flash EEPROM, having a first portion for storing a plurality of internal passwords and a second portion for storing address d... | 11/21/1995 |
| 5469565 | Personal computer for disabling resume mode upon replacement of HDD A portable computer including a CPU, a detachable hard disk pack which is connectable to a system bus of the portable computer, and a hard disk pack replacement detector which detects, in a power-OFF state, a detachment of the disk pack and sets a signal ... | 11/21/1995 |
| 5469566 | Flexible parity generation circuit for intermittently generating a parity for a plurality of data channels in a redundant array of storage units A redundant array computer system having a high-speed CPU bus and lower-speed I/O buses, in which parity blocks are generated for a plurality of data blocks from multiple CPU bus logical channels in a randomly-interleaved manner to provide enhanced I/O tr... | 11/21/1995 |
| 5469567 | System for secondary database data block buffering with block save generations and read/write access and with separate management The present invention is an improved database system for reducing the wait time for database processing programs. This data system provides for the input/output of blocks of data in excess of the capacity of the buffer pool assigned to the database proces... | 11/21/1995 |
| 5469569 | Method for detecting unauthorized modification of a communication or broadcast unit A database unit monitors the communications occurring within at least one communication system for a change status indicator of communication or broadcast units. Upon receiving the change status indicator, the database unit compares the one received with ... | 11/21/1995 |
| 5469570 | System for examining statuses of tasks when one task is interrupted in data processing system Multiple CPU's are assigned to multiple tasks on a one-to-one basis and execute corresponding tasks under the control of an operating system. Each of the CPU has a transmitter and a receiver. Each transmitter of the CPU's is connected to the receivers in ... | 11/21/1995 |
| 5469571 | Operating system architecture using multiple priority light weight kernel task based interrupt handling A software architecture is implemented through the execution of instructions by a processor. The software architecture provides a first task for performing a first function in response to the occurrence of an interrupt. The first task is assigned a first ... | 11/21/1995 |
| 5469572 | Post compile optimizer for linkable object code A system for processing a complete object code data set, to be linked into an executable program. The system features means for facilitating optimization analysis based upon the complete object code data set and also means for modifying the object code da... | 11/21/1995 |
| 5469573 | Disk operating system backup and recovery system This invention features a data backup procedure and apparatus for backing up and restoring, or otherwise loading a fully configured operating system to the high capacity storage device (e.g., hard disk) of a computer workstation, such as a personal comput... | 11/21/1995 |
| 5469574 | Method and system for interfacing interpreted applications with compiled procedures using signature files Method and system for processing an interpretable program having calls to a separately compiled procedure is described. The interpreter uses a predefined signature file (SIGFILE) to identify the arguments and result of the separately compiled procedure. T... | 11/21/1995 |
| 5469575 | Determining a winner of a race in a data processing system A first peer entity in a data processing system comprising a plurality of similar peer entities searches for a share control file for a system privilege. The share control file contains an address of a master entity which controls the system privilege. Th... | 11/21/1995 |
| 5469576 | Front end for file access controller An improved file access controller for a data processing system, and a method for the use thereof, and more particularly, an improved front end system for a file access control system, is described. The improvement is particularly useful for security audi... | 11/21/1995 |
| 5469577 | Providing alternate bus master with multiple cycles of bursting access to local bus in a dual bus system including a processor local bus and a device communications bus Disclosed method and apparatus allow for balanced usage of resources in dual bus computing systems wherein: (1) principal resources of the system--including a processor, a local bus, local bus controls, and a memory subsystem--are contained in a single sy... | 11/21/1995 |
