Inventor: Sanjeev Aggarwal

Address: Plano, TX
No. of patents: 21
Last patent issue date: 06/01/2010

Number	Title	Issue Date
7729156	Cycling to mitigate imprint in ferroelectric memories The method includes storing a memory data state in the ferroelectric memory cell. An event will trigger the evaluation of signal margin on a memory cell. If the memory cell is identified to have a weak signal, the memory cell is exercised. Exercising includes either...	06/01/2010
7514734	Hardmask for forming ferroelectric capacitors in a semiconductor device and methods for fabricating the same Hardmasks and fabrication methods are presented for producing ferroelectric capacitors in a semiconductor device, wherein a hardmask comprising aluminum oxide or strontium tantalum oxide is formed above an upper capacitor electrode material, and capacitor electrode ...	04/07/2009
7361949	Method of making a haze free, lead rich PZT film An embodiment of the invention is a method of fabricating a haze free, phase pure, PZT layer, 3, where a lead rich PZT film, 102, is formed over a phase pure stoichiometric PZT film, 101. ...	04/22/2008
7153706	Ferroelectric capacitor having a substantially planar dielectric layer and a method of manufacture therefor The present invention provides a ferroelectric capacitor, a method of manufacture therefor, and a method of manufacturing a ferroelectric random access memory (FeRAM) device. The ferroelectric capacitor (100), among other elements, includes a substantially pl...	12/26/2006
7144808	Integration flow to prevent delamination from copper The present invention provides, in one embodiment, method of forming a barrier layer 300 over a semiconductor substrate 110. The method comprises forming an opening 120 in an insulating layer 130 located over a substrate thereby uncovering an underlying copper layer...	12/05/2006
7001821	Method of forming and using a hardmask for forming ferroelectric capacitors in a semiconductor device Hardmasks and fabrication methods are presented for producing ferroelectric capacitors in a semiconductor device, wherein a hardmask comprising aluminum oxide or strontium tantalum oxide is formed above an upper capacitor electrode material, and capacitor electrode ...	02/21/2006
6995088	Surface treatment of copper to improve interconnect formation The present invention provides, in one embodiment, a method of forming a copper layer (100) over a semiconductor substrate (105). The method comprises coating a copper seed layer (110) located over a semiconductor substrate with a protective age...	02/07/2006
6984857	Hydrogen barrier for protecting ferroelectric capacitors in a semiconductor device and methods for fabricating the same Semiconductor devices and fabrication methods are presented, in which a hydrogen barrier is provided above a ferroelectric capacitor to prevent degradation of the ferroelectric material during back-end manufacturing processes employing hydrogen. The hydrogen barrier...	01/10/2006
6876021	Use of amorphous aluminum oxide on a capacitor sidewall for use as a hydrogen barrier The present invention forms sidewall diffusion barrier layer(s) that mitigate hydrogen contamination of ferroelectric capacitors. Sidewall diffusion barrier layer(s) of the present invention are formed via a physical vapor deposition process at a low temperature. By...	04/05/2005
6872669	PZT (111) texture through Ir texture improvement The present invention is directed to a method of forming a ferroelectric capacitor having a (111) PZT texture. The method includes forming a smooth bottom electrode diffusion barrier layer that facilitates a preferential (111) texture in the subsequently formed bott...	03/29/2005
6828161	Method of forming an FeRAM having a multi-layer hard mask and patterning thereof The present invention is directed to a method of forming an FeRAM integrated circuit, which includes forming a multi-layer hard mask. The multi-layer hard mask comprises a hard masking layer overlying an etch stop layer. The etch stop layer is substantially more sel...	12/07/2004
6773930	Method of forming an FeRAM capacitor having a bottom electrode diffusion barrier The present invention is directed to a method of forming an FeRAM integrated circuit, which includes forming a TiAlON bottom electrode diffusion barrier layer prior to formation of the bottom electrode layer in an FeRAM capacitor stack. Subsequently, when performing...	08/10/2004
6730354	Forming ferroelectric Pb(Zr,Ti)O3 films Improved methods of forming PZT thin films that are compatible with industry-standard chemical vapor deposition production techniques are described. These methods enable PZT thin films having thicknesses of 70 nm or less to be fabricated with high within-wafer unifo...	05/04/2004
6686236	Methods of preventing reduction of IrOx during PZT formation by metalorganic chemical vapor deposition or other processing A method of fabricating a ferroelectric capacitor is disclosed. The method comprises the decreases a reduction in a bottom electrode material during formation of the ferroelectric dielectric portion of the capacitor. In the above manner, a fatigue resista...	02/03/2004
6635498	Method of patterning a FeRAM capacitor with a sidewall during bottom electrode etch A method of fabricating a ferroelectric capacitor is disclosed. The method comprises the patterning of a top electrode layer and a dielectric layer to form a capacitor stack structure having sidewalls associated therewith. Prior to patterning the bottom e...	10/21/2003
6635497	Methods of preventing reduction of IrOx during PZT formation by metalorganic chemical vapor deposition or other processing A method of fabricating a ferroelectric capacitor is disclosed. The method comprises the decreases a reduction in a bottom electrode material during formation of the ferroelectric dielectric portion of the capacitor. In the above manner, a fatigue resista...	10/21/2003
6617178	Test system for ferroelectric materials and noble metal electrodes in semiconductor capacitors A method is provided for ferroelectric layer testing. An adhesion layer is deposited over a semiconductor substrate to be of a phase pure material lacking a first material. A lower electrode is deposited over the adhesion layer and a ferroelectric layer i...	09/09/2003
6596547	Methods of preventing reduction of IrOx during PZT formation by metalorganic chemical vapor deposition or other processing A method of fabricating a ferroelectric capacitor is disclosed. The method comprises decreasing a reduction in a bottom electrode material during formation of the ferroelectric dielectric portion of the capacitor. The method comprises forming an oxygen do...	07/22/2003
6576482	One step deposition process for the top electrode and hardmask in a ferroelectric memory cell One aspect of the invention relates to a one-step process for forming a transition metal aluminum oxynitride layer over a transition metal aluminum nitride layer. The transition metal aluminum nitride layer is sputter deposited using a transition metal/al...	06/10/2003
6528328	Methods of preventing reduction of irox during PZT formation by metalorganic chemical vapor deposition or other processing A method of fabricating a ferroelectric capacitor is disclosed. The method comprises the decreases a reduction in a bottom electrode material during formation of the ferroelectric dielectric portion of the capacitor. In the above manner, a fatigue resista...	03/04/2003
6500678	Methods of preventing reduction of IrOx during PZT formation by metalorganic chemical vapor deposition or other processing A method of fabricating a ferroelectric capacitor is disclosed. The method comprises the decreases a reduction in a bottom electrode material during formation of the ferroelectric dielectric portion of the capacitor. In the above manner, a fatigue resista...	12/31/2002

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Inventor: Sanjeev Aggarwal