Inventor: Yaocheng Liu

Address: Elmsford, NY
No. of patents: 19
Last patent issue date: 07/10/2012

Number	Title	Issue Date
8217423	Structure and method for mobility enhanced MOSFETs with unalloyed silicide While embedded silicon germanium alloy and silicon carbon alloy provide many useful applications, especially for enhancing the mobility of MOSFETs through stress engineering, formation of alloyed silicide on these surfaces degrades device performance. The present in...	07/10/2012
7932144	Semiconductor structure and method of forming the structure Disclosed are embodiments of an n-FET structure with silicon carbon S/D regions completely contained inside amorphization regions and with a carbon-free gate electrode. Containing carbon within the amorphization regions, ensures that all of the carbon is substitutio...	04/26/2011
7888197	Method of forming stressed SOI FET having doped glass box layer using sacrificial stressed layer A method is provided for fabricating a semiconductor-on-insulator (“SOI”) substrate. In such method an SOI substrate is formed to include (i) an SOI layer of monocrystalline silicon separated from (ii) a bulk semiconductor layer by (iii) a buried oxide (“BOX�...	02/15/2011
7838932	Raised STI structure and superdamascene technique for NMOSFET performance enhancement with embedded silicon carbon An embedded silicon carbon (Si:C) having a substitutional carbon content in excess of one percent in order to effectively increase electron mobility by application of tension to a channel region of an NFET is achieved by overfilling a gap or trench formed by transis...	11/23/2010
7741658	Self-aligned super stressed PFET The embodiments of the invention comprise a self-aligned super stressed p-type field effect transistor (PFET). More specifically, a field effect transistor comprises a channel region comprising N-doped material and a gate above the channel region. The field effect t...	06/22/2010
7714358	Semiconductor structure and method of forming the structure Disclosed are embodiments of an n-FET structure with silicon carbon S/D regions completely contained inside amorphization regions and with a carbon-free gate electrode. Containing carbon within the amorphization regions, ensures that all of the carbon is substitutio...	05/11/2010
7709910	Semiconductor structure for low parasitic gate capacitance A semiconductor structure provides lower parasitic capacitance between the gate electrode and contact vias while providing substantially the same level of stress applied by a nitride liner as conventional MOSFETs by reducing the height of the gate electrode and main...	05/04/2010
7696000	Low defect Si:C layer with retrograde carbon profile Formation of carbon-substituted single crystal silicon layer is prone to generation of large number of defects especially at high carbon concentration. The present invention provides structures and methods for providing low defect carbon-substituted single crystal s...	04/13/2010
7675118	Semiconductor structure with enhanced performance using a simplified dual stress liner configuration A semiconductor structure including an nFET having a fully silicided gate electrode wherein a new dual stress liner configuration is used to enhance the stress in the channel region that lies beneath the gate electrode is provided. The new dual stress liner configur...	03/09/2010
7667263	Semiconductor structure including doped silicon carbon liner layer and method for fabrication thereof A semiconductor structure and related method for fabrication thereof includes a liner layer interposed between: (1) a pedestal shaped channel region within a semiconductor substrate; and (2) a source region and a drain region within a semiconductor material layer lo...	02/23/2010
7655551	Control of poly-Si depletion in CMOS via gas phase doping A method to control the poly-Si depletion effect in CMOS structures utilizing a gas phase doping process which is capable of providing a high concentration of dopant atoms at the gate dielectric/poly-Si interface is provided. The present invention also provides CMOS...	02/02/2010
7632724	Stressed SOI FET having tensile and compressive device regions A method is provided for fabricating a field effect transistor (“FET”) having a channel region in a semiconductor-on-insulator (“SOI”) layer of an SOI substrate. Desirably, in such method, a sacrificial stressed layer is formed to overlie a first portion of ...	12/15/2009
7615435	Semiconductor device and method of manufacture A semiconductor device and method of manufacture and, more particularly, a semiconductor device having strain films and a method of manufacture. The device includes an embedded SiGeC layer in source and drain regions of an NFET device and an embedded SiGe layer in s...	11/10/2009
7504309	Pre-silicide spacer removal A method forms a gate conductor over a substrate, and simultaneously forms spacers on sides of the gate conductor and a gate cap on the top of the gate conductor. Isolation regions are formed in the substrate and the method implants an impurity into exposed regions ...	03/17/2009
7485519	After gate fabrication of field effect transistor having tensile and compressive regions A field effect transistor (“FET”) is formed to include a stress in a channel region of an active semiconductor region of an SOI substrate. A gate is formed to overlie the active semiconductor region, after which a sacrificial stressed layer is formed which overl...	02/03/2009
7473594	Raised STI structure and superdamascene technique for NMOSFET performance enhancement with embedded silicon carbon An embedded silicon carbon (Si:C) having a substitutional carbon content in excess of one percent in order to effectively increase electron mobility by application of tension to a channel region of an NFET is achieved by overfilling a gap or trench formed by transis...	01/06/2009
7473608	N-channel MOSFETs comprising dual stressors, and methods for forming the same The present invention relates to a semiconductor device comprising at least one n-channel field effect transistor (n-FET). Specifically, the n-FET comprises first and second patterned stressor layers that both contain a carbon-substituted and tensilely stressed sing...	01/06/2009
7473626	Control of poly-Si depletion in CMOS via gas phase doping A method to control the poly-Si depletion effect in CMOS structures utilizing a gas phase doping process which is capable of providing a high concentration of dopant atoms at the gate dielectric/poly-Si interface is provided. The present invention also provides CMOS...	01/06/2009
7279758	N-channel MOSFETs comprising dual stressors, and methods for forming the same The present invention relates to a semiconductor device including at least one n-channel field effect transistor (n-FET). Specifically, the n-FET includes first and second patterned stressor layers that both contain a carbon-substituted and tensilely stressed single...	10/09/2007

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Inventor: Yaocheng Liu