Inventor: Wei Chen

Address: Croton-on-Hudson, NY
No. of patents: 4
Last patent issue date: 06/20/2000

Number	Title	Issue Date
6078195	Logic blocks with mixed low and regular V_t MOSFET devices for VLSI design in the deep sub-micron regime Logic books with mixed low Vt and regular Vt devices provide a performance gain without the large increase in stand-by power of the logic book. Low Vt devices are used to gain speed, and regular Vt devices are u...	06/20/2000
5937295	Nano-structure memory device A memory device and memory incorporating a plurality of the memory devices is described wherein each memory device has spaced apart source and drain regions, a channel, a barrier insulating layer, a nanocrystal or a plurality of nanocrystals, a control ba...	08/10/1999
5767549	SOI CMOS structure An integrated circuit is described incorporating a substrate, a layer of insulator, a layer of silicon having raised mesas and thin regions therebetween to provide ohmic conduction between mesas, electronic devices on the mesas, and interconnection wiring...	06/16/1998
5714766	Nano-structure memory device A memory device and memory incorporating a plurality of the memory devices is described wherein each memory device has spaced apart source and drain regions, a channel, a barrier insulating layer, a nanocrystal or a plurality of nanocrystals, a control ba...	02/03/1998

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