Inventor: Uday Shah

Address: Portland, OR
No. of patents: 66
Last patent issue date: 01/01/2013

Number	Title	Issue Date
8344425	Multi-gate III-V quantum well structures Methods of forming microelectronic structures are described. Embodiments of those methods include forming a III-V tri-gate fin on a substrate, forming a cladding material around the III-V tri-gate fin, and forming a hi k gate dielectric around the cladding material....	01/01/2013
8334184	Polish to remove topography in sacrificial gate layer prior to gate patterning Techniques are disclosed for fabricating FinFET transistors (e.g., double-gate, trigate, etc). A sacrificial gate material (such as polysilicon or other suitable material) is deposited on fin structure, and polished to remove topography in the sacrificial gate mater...	12/18/2012
8283653	Non-planar germanium quantum well devices Techniques are disclosed for forming a non-planar germanium quantum well structure. In particular, the quantum well structure can be implemented with group IV or III-V semiconductor materials and includes a germanium fin structure. In one example case, a non-planar ...	10/09/2012
8269209	Isolation for nanowire devices The present disclosure relates to the field of fabricating microelectronic devices. In at least one embodiment, the present disclosure relates to forming an isolated nanowire, wherein isolation structure adjacent the nanowire provides a substantially level surface f...	09/18/2012
8264048	Multi-gate device having a T-shaped gate structure A multi-gate device having a T-shaped gate structure is generally described. In one example, an apparatus includes a semiconductor substrate, at least one multi-gate fin coupled with the semiconductor substrate, the multi-gate fin having a gate region, a source regi...	09/11/2012
8193567	Process for integrating planar and non-planar CMOS transistors on a bulk substrate and article made thereby A process capable of integrating both planar and non-planar transistors onto a bulk semiconductor substrate, wherein the channel of all transistors is definable over a continuous range of widths. ...	06/05/2012
8168508	Method of isolating nanowires from a substrate A method is provided. The method includes forming a plurality of nanowires on a top surface of a substrate and forming an oxide layer adjacent to a bottom surface of each of the plurality of nanowires, wherein the oxide layer is to isolate each of the plurality of n...	05/01/2012
8119508	Forming integrated circuits with replacement metal gate electrodes In a metal gate replacement process, a stack of at least two polysilicon layers or other materials may be formed. Sidewall spacers may be formed on the stack. The stack may then be planarized. Next, the upper layer of the stack may be selectively removed. Then, the ...	02/21/2012
8071983	Semiconductor device structures and methods of forming semiconductor structures A method of patterning a semiconductor film is described. According to an embodiment of the present invention, a hard mask material is formed on a silicon film having a global crystal orientation wherein the semiconductor film has a first crystal plane and second cr...	12/06/2011
8067818	Nonplanar device with thinned lower body portion and method of fabrication A nonplanar semiconductor device having a semiconductor body formed on an insulating layer of a substrate. The semiconductor body has a top surface opposite a bottom surface formed on the insulating layer and a pair of laterally opposite sidewalls wherein the distan...	11/29/2011
8030197	Recessed channel array transistor (RCAT) in replacement metal gate (RMG) logic flow Embodiments of the invention relate to a method of fabricating logic transistors using replacement metal gate (RMG) logic flow with modified process to form recessed channel array transistors (RCAT) on a common semiconductor substrate. An embodiment comprises formin...	10/04/2011
8030163	Reducing external resistance of a multi-gate device using spacer processing techniques A method includes depositing a sacrificial gate electrode to one or more multi-gate fins. The sacrificial gate electrode is patterned such that it is coupled to a gate region and substantially no sacrificial gate electrode is coupled to source and drain regions. A d...	10/04/2011
7898041	Block contact architectures for nanoscale channel transistors A contact architecture for nanoscale channel devices having contact structures coupling to and extending between source or drain regions of a device having a plurality of parallel semiconductor bodies. The contact structures being able to contact parallel semiconduc...	03/01/2011
7883951	CMOS device with metal and silicide gate electrodes and a method for making it A semiconductor device and a method for forming it are described. The semiconductor device comprises a metal NMOS gate electrode that is formed on a first part of a substrate, and a silicide PMOS gate electrode that is formed on a second part of the substrate. ...	02/08/2011
7825437	Unity beta ratio tri-gate transistor static random access memory (SRAM) In general, in one aspect, a method includes forming N-diffusion and P-diffusion fins in a semiconductor substrate. A P-diffusion gate layer is formed over the semiconductor substrate and removed from the N-diffusion fins. A pass-gate N-diffusion gate layer is forme...	11/02/2010
7820512	Spacer patterned augmentation of tri-gate transistor gate length In general, in one aspect, a method includes forming a semiconductor substrate having N-diffusion and P-diffusion regions. A gate stack is formed over the semiconductor substrate. A gate electrode hard mask is formed over the gate stack. The gate electrode hard mask...	10/26/2010
7785958	Method for making a semiconductor device having a high-k gate dielectric layer and a metal gate electrode A method for making a semiconductor device is described. That method comprises forming a first dielectric layer on a substrate, a trench within the first dielectric layer, and a second dielectric layer on the substrate. The second dielectric layer has a first part t...	08/31/2010
7763943	Reducing external resistance of a multi-gate device by incorporation of a partial metallic fin Reducing external resistance of a multi-gate device by incorporation of a partial metallic fin is generally described. In one example, an apparatus includes a semiconductor substrate and one or more fins of a multi-gate transistor device coupled with the semiconduct...	07/27/2010
7745270	Tri-gate patterning using dual layer gate stack In general, in one aspect, a method includes forming an n-diffusion fin and a p-diffusion fin in a semiconductor substrate. A high dielectric constant layer is formed over the substrate. A first work function metal layer is created over the n-diffusion fin and a sec...	06/29/2010
7718479	Forming integrated circuits with replacement metal gate electrodes In a metal gate replacement process, a stack of at least two polysilicon layers or other materials may be formed. Sidewall spacers may be formed on the stack. The stack may then be planarized. Next, the upper layer of the stack may be selectively removed. Then, the ...	05/18/2010
7709312	Methods for inducing strain in non-planar transistor structures Methods for inducing compressive strain in channel region of a non-planar transistor and devices and systems formed by such methods. In one embodiment, a method can include forming trenches in a semiconductor body adjacent to gate structure spacers. The semiconducto...	05/04/2010
7704835	Method of forming a selective spacer in a semiconductor device A selective spacer for semiconductor and MEMS devices and method of manufacturing the same. In an embodiment, a selective spacer is formed adjacent to a first non-planar body having a greater sidewall height than a second non-planar semiconductor body in a self-alig...	04/27/2010
7700470	Selective anisotropic wet etching of workfunction metal for semiconductor devices Embodiments of an apparatus and methods for providing a workfunction metal gate electrode on a substrate with doped metal oxide semiconductor structures are generally described herein. Other embodiments may be described and claimed. ...	04/20/2010
7671471	Method for making a semiconductor device having a high-k dielectric layer and a metal gate electrode A method for making a semiconductor device is described. That method comprises forming a first dielectric layer on a substrate, then forming a trench within the first dielectric layer. After forming a second dielectric layer on the substrate, a first metal layer is ...	03/02/2010
7666796	Substrate patterning for multi-gate transistors Some embodiments of the present invention include apparatuses and methods relating to improved substrate patterning for multi-gate transistors. ...	02/23/2010
7615441	Forming high-k dielectric layers on smooth substrates A buffer layer and a high-k metal oxide dielectric may be formed over a smooth silicon substrate. The substrate smoothness may reduce column growth of the high-k metal oxide gate dielectric. The surface of the substrate may be saturated with hydroxyl terminations pr...	11/10/2009
7579280	Method of patterning a film A method of patterning a thin film. The method includes forming a mask on a film to be patterned. The film is then etched in alignment with the mask to form a patterned film having a pair of laterally opposite sidewalls. A protective layer is formed on the pair of l...	08/25/2009
7575976	Localized spacer for a multi-gate transistor In one embodiment, the present invention includes a double gate transistor having a silicon fin formed on a buried oxide layer and first and second insulation layers formed on a portion of the silicon fin, where at least the second insulation layer has a pair of por...	08/18/2009
7550333	Nonplanar device with thinned lower body portion and method of fabrication A nonplanar semiconductor device having a semiconductor body formed on an insulating layer of a substrate. The semiconductor body has a top surface opposite a bottom surface formed on the insulating layer and a pair of laterally opposite sidewalls wherein the distan...	06/23/2009
7547637	Methods for patterning a semiconductor film A method of patterning a semiconductor film is described. According to an embodiment of the present invention, a hard mask material is formed on a silicon film having a global crystal orientation wherein the semiconductor film has a first crystal plane and second cr...	06/16/2009
7531437	Method of forming metal gate electrodes using sacrificial gate electrode material and sacrificial gate dielectric material A semiconductor device comprising a semiconductor body having a top surface and a first and second laterally opposite sidewalls as formed on an insulating substrate is claimed. A gate dielectric is formed on the top surface of the semiconductor body and on the first...	05/12/2009
7528025	Nonplanar transistors with metal gate electrodes A semiconductor device comprising a semiconductor body having a top surface and a first and second laterally opposite sidewalls as formed on an insulating substrate is claimed. A gate dielectric is formed on the top surface of the semiconductor body and on the first...	05/05/2009
7521775	Protection of three dimensional transistor structures during gate stack etch Embodiments of the invention include apparatuses and methods relating to three dimensional transistors having high-k dielectrics and metal gates with fins protected by a hard mask layer on their top surface. In one embodiment, the hard mask layer includes an oxide.	04/21/2009
7479421	Process for integrating planar and non-planar CMOS transistors on a bulk substrate and article made thereby A process capable of integrating both planar and non-planar transistors onto a bulk semiconductor substrate, wherein the channel of all transistors is definable over a continuous range of widths. ...	01/20/2009
7435683	Apparatus and method for selectively recessing spacers on multi-gate devices Embodiments of an apparatus and methods for fabricating a spacer on one part of a multi-gate transistor without forming a spacer on another part of the multi-gate transistor are generally described herein. Other embodiments may be described and claimed. ...	10/14/2008
7425490	Reducing reactions between polysilicon gate electrodes and high dielectric constant gate dielectrics In a metal gate replacement process, a gate electrode stack may be formed of a dielectric covered by a sacrificial metal layer covered by a polysilicon gate electrode. In subsequent processing of the source/drains, high temperature steps may be utilized. The sacrifi...	09/16/2008
7414290	Double gate transistor, method of manufacturing same, and system containing same A double gate transistor comprises a substrate (105, 905) and first and second electrically insulating layers (110, 910), (120, 920). The first and second electrically insulating layers form a fin (130, 930). A first gate dielectric (1...	08/19/2008
7407847	Stacked multi-gate transistor design and method of fabrication A multi-body thickness (MBT) field effect transistor (FET) comprises a silicon body formed on a substrate. The silicon body may comprise a wide section and a narrow section between the wide section and the substrate. The silicon body may comprise more than one pair ...	08/05/2008
7396711	Method of fabricating a multi-cornered film Embodiments of the present invention describe a method of forming a multi-cornered film. According to the embodiments of the present invention, a photoresist mask is formed on a hard mask film formed on a film. The hard mask film is then patterned in alignment with ...	07/08/2008
7390947	Forming field effect transistors from conductors A nanotube transistor, such as a carbon nanotube transistor, may be formed with a top gate electrode and a spaced source and drain. Conduction along the transistor from source to drain is controlled by the gate electrode. Underlying the gate electrode are at least t...	06/24/2008

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Inventor: Uday Shah