|7471579||Semiconductor memory and test method for the same|
In a semiconductor memory, a sub bit line hierarchical switch is provided correspondingly to each sub bit line between the sub bit line and a main bit line corresponding to the sub bit line, and a complementary sub bit line hierarchical switch is provided correspond...
|7038967||Semiconductor apparatus capable of performing refresh control|
A semiconductor apparatus according to the present invention comprises a current source increasing a current volume in compliance with a rise of a temperature and an oscillation circuit driven by the current of the current source and outputting a clock for refresh c...
|6483763||Semiconductor memory device|
Each of a plurality of sense amplifiers in a sense amplifier drive circuit of a DRAM includes a PMOS sense amplifier drive transistor and an NMOS sense amplifier drive transistor. The source of each of the PMOS sense amplifier drive transistors is connect...