Inventor: Terry J. Parks

Address: Round Rock, TX
No. of patents: 39
Last patent issue date: 09/28/1999

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Number	Title	Issue Date
5959923	Digital computer having a system for sequentially refreshing an expandable dynamic RAM memory circuit A digital computer which includes a memory refresh system for controlling the generation and sequencing of refresh signals to a memory subsystem comprised of at least one memory unit having a plurality of slots each capable of receiving a dynamic random a...	09/28/1999
5862369	Method and apparatus for state machine optimization using device delay characteristics A method and apparatus which enables circuitry to detect and take advantage of the intrinsic performance or delay characteristic of the respective device in which the circuitry is embedded. By determining the delay characteristics of the device and sampli...	01/19/1999
5708794	Multi-purpose usage of transaction backoff and bus architecture supporting same A digital processor system is disclosed that employs a bus bridge interfacing a primary bus to a secondary bus and which includes a transaction backoff signal line that provides an economical method of providing split transactions between the busses, of p...	01/13/1998
5640517	Method and apparatus for masters to command a slave whether to transfer data in a sequential or non-sequential burst order A bus with selective burst ordering enables the implementation of computer systems that incorporate bus masters (e.g., processors, DMA controllers, LAN controllers, etc.) with dissimilar burst orders. The same bus supports devices which require or prefer ...	06/17/1997
5638527	System and method for memory mapping A memory mapping scheme for a computer system includes a number of slave devices attached to a system bus, which slave devices have partitioned among themselves a memory address storage system. The memory address storage system is, in turn, divided into a...	06/10/1997
5623700	Interface circuit having zero latency buffer memory and cache memory information transfer A caching disk controller is provided which includes a bus bridge that forms an interface between a memory of the disk controller and a host computer. The caching disk controller further includes a SCSI processor for controlling the transfer of data from ...	04/22/1997
5619723	System for scheduling read ahead operations if new request is sequential of last n last read requests wherein n is different on independent activities A disk drive array with a controller which provides: dynamic remapping for grown defects in the disk drives, multi-thread request processing with a variable number of forkings, defect tracking with both logical and physical lists, guarded writes of less t...	04/08/1997
5600801	Multiple function interface device for option card A device for interfacing an expansion bus with an option card and an associated method for initializing a computer system having the option card installed on the expansion bus thereof. The interface device includes a dual ported RAM having a first port co...	02/04/1997
5592684	Store queue including a byte order tracking mechanism for maintaining data coherency A store queue is provided that forms an interface between a primary bus and a secondary bus and which temporarily stores data to be written via a memory or I/O channel to a peripheral device. The store queue allows partial writes executed on the primary b...	01/07/1997
5590287	Configurable interface for routing data between mismatched devices A digital computer system includes an interface for routing data which permits the transfer of data between mismatched devices. The computer system comprises a processor, memory and an interconnecting data bus, all configured to handle data units of a fir...	12/31/1996
5590338	Combined multiprocessor interrupt controller and interprocessor communication mechanism A combined multiprocessor interrupt controller and interprocessor communication mechanism includes a system bus, an input/output bridge element coupled to the system bus, and a system controller coupled to the system bus. The input/output bridge element i...	12/31/1996
5555395	System for memory table cache reloads in a reduced number of cycles using a memory controller to set status bits in the main memory table A method and apparatus for reducing the latency of TLB and segment descriptor reloads by eliminating the extra read/write cycles normally required for these accesses. The CPU includes special cycles which perform segment descriptor and TLB reloads using o...	09/10/1996
5530960	Disk drive controller accepting first commands for accessing composite drives and second commands for individual diagnostic drive control wherein commands are transparent to each other A disk drive array with a controller which provides: dynamic remapping for grown defects in the disk drives, multi-thread request processing with a variable number of forkings, defect tracking with both logical and physical lists, guarded writes of less t...	06/25/1996
5526481	Display scrolling system for personal digital assistant A display scrolling system for a personal digital assistant (PDA) which includes a display screen disposed on a top surface of the PDA and a mouse integrated into the bottom surface of the PDA. Documents to be displayed on the screen are stored in a memor...	06/11/1996
5524248	Random access memory power management system Method and apparatus for power management of a RAM subsystem of a computer. Blocks of data stored at various addresses throughout the RAM subsystem are packed into unallocated memory space at the lowest possible physical location within the RAM subsystem ...	06/04/1996
5517671	System for designating a plurality of I/O devices to a plurality of I/O channels and connecting and buffering the plurality of I/O channels to a single system bus A system for connecting a plurality of input/output (I/O) channels to a single computer system bus. A system controller establishes priority among the I/O channels competing for access to the system bus. A plurality of I/O channel bridges are connected to...	05/14/1996
5483641	System for scheduling readahead operations if new request is within a proximity of N last read requests wherein N is dependent on independent activities An improved read ahead strategy that improves the performance of a disk array subsystem. The disk controller keeps track of the last n reads to the array. If a new read request is received that is adjacent to any of the last n reads, the controller perfor...	01/09/1996
5483260	Method and apparatus for simplified video monitor control A method and apparatus which provides bi-directional communication between a video monitor and a computer system unit. This enables the video monitor to inform the system unit of its capabilities without direct user involvement and also enables the system...	01/09/1996
5477237	Positioning device reporting X, Y and yaw motion A pointing device or mouse which monitors motion in both the X and Y directions as well as in the yaw or rotational direction. The pointing device hence monitors three degrees of freedom and thus provides a more accurate indication of the position of the ...	12/19/1995
5477551	Apparatus and method for optimal error correcting code to parity conversion This invention relates to the general area of data integrety in digital computers. In particular it relates to digital computer systems having parity checked systems busses and ECC checked memory. This invention increases the performance of such systems b...	12/19/1995
5473761	Controller for receiving transfer requests for noncontiguous sectors and reading those sectors as a continuous block by interspersing no operation requests between transfer requests A disk drive array including a controller which provides scatter/scatter (bi-directional scatter/gather) operations between noncontiguous host memory address locations and noncontiguous disk address locations. The host provides a single request to launch ...	12/05/1995
5471225	Liquid crystal display with integrated frame buffer An improved liquid crystal display (LCD) is provided having a static random access memory located within each liquid crystal control cell and between each display electrode and corresponding bit and word lines. The memory cell, or storage cell, includes a...	11/28/1995
5469559	Method and apparatus for refreshing a selected portion of a dynamic random access memory A system for refreshing selected portions of a dynamic access memory (DRAM) subsystem of a computer. A memory controller of the present invention includes a RAM device for storing a plurality of region descriptors used to inhibit the refresh of address ra...	11/21/1995
5465346	Method and apparatus for synchronous bus interface optimization A method and apparatus which enables devices connected to a bus to detect and take advantage of the early arrival of bus signal inputs. A signal arrival encoder circuit included in a device encodes the arrival time of a signal input whose early arrival is...	11/07/1995
5463643	Redundant memory channel array configuration with data striping and error correction capabilities A memory channel array configuration wherein two or more memory channels are used for data transfer and data is striped across each of the memory channels. In addition, one or more redundant memory channels, preferably a single dedicated parity channel, a...	10/31/1995
5455466	Inductive coupling system for power and data transfer A system for inductively coupling power and data to a portable electronic device. A portable device, such as a personal digital assistant, is powered or recharged via an inductive link between the device and a support unit, thereby eliminating the need fo...	10/03/1995
5452463	Processor and cache controller interface lock jumper A computer system including at least one processor and a cache subsystem, in which computer system locked cycles are generated, include a jumper assembly for operatively connecting the at least one processor and the cache subsystem so as to render locked ...	09/19/1995
5448697	Method and apparatus for simplified control of a video monitor A method and apparatus which provides bi-directional communication between a video monitor and a computer system unit. This enables the video monitor to inform the system unit of its capabilities without user involvement and also enables the system unit t...	09/05/1995
5404454	Method for interleaving computer disk data input-out transfers with permuted buffer addressing An apparatus and method for a computer system having at least two disk drives in a data storage system wherein data may be read from or written to the disk drives simultaneously during a load multiple operation. Data from the disk drives may be simultaneo...	04/04/1995
5384788	Apparatus and method for optimal error correcting code to parity conversion This invention relates to the general area of data integrety in digital computers. In particular it relates to digital computer systems having parity checked systems busses and ECC checked memory. This invention increases the performance of such systems b...	01/24/1995
5369605	Incremental search content addressable memory for increased data compression efficiency A content addressable memory (CAM) which is capable of performing string search functions in hardware. The implementation of string search in hardware eliminates the requirement of software to perform this function and thus significantly increases data co...	11/29/1994
5359611	Method and apparatus for reducing partial write latency in redundant disk arrays An apparatus and method for a computer system having at least three disk drives in a storage array in which the rotational speed and angular position of the disk spindles are synchronized. At least two of these disks store data and at least one disk store...	10/25/1994
5357622	Apparatus for queing and storing data writes into valid word patterns A digital computer system has a central processor unit (CPU) and a store queue facility. The store queue facility receives full digital words or segments thereof (bytes) for intermediate storage prior to storage in an addressable unit such as a dynamic ra...	10/18/1994
5355251	Liquid crystal display device with octagonal cell providing increased wiring density A liquid crystal display (LCD) of high visual quality and having a high density wiring arrangement is provided. The LCD can accommodate up to four addressing and/or control conductors placed across the display and between columns and rows of display elect...	10/11/1994
5325508	Processor that performs memory access in parallel with cache access A computer system includes an accessible memory controller, an accessible cache controller, and circuitry for accessing the accessible memory controller and the accessible cache controller simultaneously. Certain preferred embodiments of the present inven...	06/28/1994
5261068	Dual path memory retrieval system for an interleaved dynamic RAM memory unit A digital computer having a dual path memory retrieval system for a dynamic RAM memory unit comprised of any number of interleaved memory banks. The system includes means for asserting and deasserting an access signal to specified locations of the interle...	11/09/1993
5239445	Method and apparatus for simultaneous operation of two IDE disk drives An apparatus and method for a computer system to rapidly access at least two IDE disk drives. Use of standard forty pin connectors and forty wire ribbon cable having certain pairs of wires uniquely twisted so as to allow the system to independently access...	08/24/1993
5163145	Circuit for determining between a first or second type CPU at reset by examining upper M bits of initial memory reference A computer system provides a RESET-signal for resetting registers upon start-up of the system, and includes a central processor unit (CPU) of an optional type and a detect circuit for determining which optional type. On start-up, the CPU sends out an init...	11/10/1992
5099196	On-chip integrated circuit speed selection An electronic circuit for the detection of required operational speed of one or more integrated circuit semiconductor chips is used in conjunction with an off-the-shelf integrated circuit tester. The tester provides timing, control and a display. Each of ...	03/24/1992

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Inventor: Terry J. Parks

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