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Inventor: TR Ramesh


Address: Newark, CA
No. of patents: 1
Last patent issue date: 06/10/2003

NumberTitleIssue Date
6578134Multi-branch resolution
A branch resolution logic for an in-order processor is provided which scans the stages of processor pipeline to determine the oldest branch instruction having sufficient condition codes for resolution. The stages are scanned in order from the latter stage...
06/10/2003
 
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