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| Number | Title | Issue Date |
| 8341578 | Clock gater with test features and low setup time A clock gater circuit comprises a plurality of transistors having source-drain connections forming a stack between a first node and a supply node. A given logical state on the first node causes a corresponding logical state on an output clock of the clock gater circ... | 12/25/2012 |
| 8219946 | Method for clock gating circuits In one embodiment, a method is provided for generating clock gating circuitry for a circuit design model. A Boolean expression of path sensitization is determined for each gate element in the netlist of a circuit design. For each gate element, a conjunction of the B... | 07/10/2012 |
| 8099703 | Method and system for verifying power-optimized electronic designs using equivalency checking Embodiments of the present invention provide methods and systems for verifying functional equivalence of a power optimized design and its original, unoptimized design (referred to as the golden design) using combinational equivalency checking. Due to some inherent l... | 01/17/2012 |
| 7779372 | Clock gater with test features and low setup time A clock gater circuit comprises a plurality of transistors having source-drain connections forming a stack between a first node and a supply node. A given logical state on the first node causes a corresponding logical state on an output clock of the clock gater circ... | 08/17/2010 |
| 7746116 | Method and apparatus to clock-gate a digital integrated circuit by use of feed-forward quiescent input analysis One aspect of the invention relates to a device including a first storage element and a first clock gating element, wherein a data input of the first storage element is coupled to an output of a combinatorial logic (CL) element, wherein the first storage element is ... | 06/29/2010 |
| 7055135 | Method for debugging an integrated circuit Embodiments of the present invention provide a method and apparatus for debugging an integrated circuit. In particular, one embodiment of the present invention includes steps of: (a) retrieving data from a design data base, and creating a design pattern in a pattern... | 05/30/2006 |
| 6658632 | Boundary scan cell architecture with complete set of operational modes for high performance integrated circuits An electrical circuit includes a flip-flop, a first multiplexer, a second flip-flop, a third flip-flop, and output storage element including a second multiplexer and a fourth flip-flop. The first flip-flop, clocked functional clock signal, receives a func... | 12/02/2003 |
| 6578168 | Method for operating a boundary scan cell design for high performance I/O cells A boundary scan cell design which places the multiplexor before the functional flip-flip on the functional line path, reducing the multiplexor delay in the critical path. This optimizes the multiplexor and functional flip-flop orientation, allowing for a ... | 06/10/2003 |
| 6567944 | Boundary scan cell design for high performance I/O cells A boundary scan cell design which places the multiplexor before the functional flip-flip on the functional line path, reducing the multiplexor delay in the critical path. This optimizes the multiplexor and functional flip-flop orientation, allowing for a ... | 05/20/2003 |
| 6507925 | Spatial and temporal alignment of a scan dump for debug of scan-based designs A method for analyzing a scan dump assigns a first latch to a first value, compares the first latch output to the first value for spatial alignment. The method then assigns a second latch to either a second or third value. The second value corresponds to ... | 01/14/2003 |
| 6452423 | Circuit for avoiding contention in one-hot or one-cold multiplexer designs A circuit for avoiding contention in such circuits as an n-to-1 transmission gate multiplexer in a high performance microprocessor or integrated circuit utilizes a same-gate symmetrical design and reverse polarity control signals to overcome disadvantages... | 09/17/2002 |
| 6081913 | Method for ensuring mutual exclusivity of selected signals during application of test patterns A method for controlling a gating circuit of an electronic system incorporating a scan architecture complying with IEEE Standard 1149.1 such that the gating circuit applies mutually exclusive signals to, for example, a decoded multiplexer. The gating circ... | 06/27/2000 |
| 5898702 | Mutual exclusivity circuit for use in test pattern application scan architecture circuits A circuit for locally ensuring mutual exclusivity of selected signals during scan testing is coupled between an IEEE 1149.1 TAP controller and a conventional gating circuit. The mutual exclusivity circuit includes an AND-gate, an inverter, a first scan fl... | 04/27/1999 |
