Inventor: Simon Chooi

Address: Singapore, SG
No. of patents: 90
Last patent issue date: 11/18/2008

Number	Title	Issue Date
7452808	Method of copper/copper surface bonding using a conducting polymer for application in IC chip bonding A semiconductor chip having an exposed metal terminating pad thereover, and a separate substrate having a corresponding exposed metal bump thereover are provided. A conducting polymer plug is formed over the exposed metal terminating pad. A conforming interface laye...	11/18/2008
7268048	Methods for elimination of arsenic based defects in semiconductor devices with isolation regions Methods of preparing conductive regions such as source/drain regions for silicidation procedures, has been developed. The methods feature removal of native oxide as well as removal of deposited arsenic based defects from conductive surfaces prior to deposition of a ...	09/11/2007
7186640	Silicon-rich oxide for copper damascene interconnect incorporating low dielectric constant dielectrics A method of fabricating at least one damascene opening comprising the following steps. A structure having at least one exposed conductive structure is provided. A dielectric barrier layer over the structure and the at least one exposed conductive structure. A lower ...	03/06/2007
7179879	Poly(arylene ether) dielectrics The present invention relates to poly(arylene ethers) used as low k dielectric layers in electronic applications and articles containing such poly(arylene ethers) comprising the structure: wherein n=5 to 10000 an...	02/20/2007
7166250	Poly(arylene ether) dielectrics The present invention relates to poly(arylene ethers) used as low k dielectric layers in electronic applications and articles containing such poly(arylene ethers) comprising the structure: wherein n=5 to 10000 an...	01/23/2007
7071281	Poly(arylene ether) dielectrics The present invention relates to poly(arylene ethers) used as low k dielectric layers in electronic applications and articles containing such poly(arylene ethers) comprising the structure: wherein n=5 to 10000 an...	07/04/2006
7060613	Method of copper/copper surface bonding using a conducting polymer for application in IC chip bonding A semiconductor chip having an exposed metal terminating pad thereover, and a separate substrate having a corresponding exposed metal bump thereover are provided. A conducting polymer plug is formed over the exposed metal terminating pad. A conforming interface laye...	06/13/2006
7005716	Dual metal gate process: metals and their silicides Methods for forming dual-metal gate CMOS transistors are described. An NMOS and a PMOS active area of a semiconductor substrate are separated by isolation regions. A metal layer is deposited over a gate dielectric layer in each active area. Silicon ions are implante...	02/28/2006
6987321	Copper diffusion deterrent interface Method and product for forming a dual damascene interconnect structure, wherein depositing a copper sulfide interface layer as sidewalls to the opening deters migration or diffusing of copper ions into the dielectric material. ...	01/17/2006
6967162	Method of copper/copper surface bonding using a conducting polymer for application in IC chip bonding A semiconductor chip having an exposed metal terminating pad thereover, and a separate substrate having a corresponding exposed metal bump thereover are provided. A conducting polymer plug is formed over the exposed metal terminating pad. A conforming interface laye...	11/22/2005
6891233	Methods to form dual metal gates by incorporating metals and their conductive oxides Methods for forming dual-metal gate CMOS transistors are described. An NMOS and a PMOS active area of a semiconductor substrate are separated by isolation regions. A metal layer is deposited over a gate dielectric layer in each active area. Oxygen ions are implanted...	05/10/2005
6846899	Poly(arylene ether) dielectrics The present invention relates to poly(arylene ethers) used as low k dielectric layers in electronic applications and articles containing such poly(arylene ethers) comprising the structure: wherein n=5 to 10000 and mono...	01/25/2005
6835989	Methods to form dual metal gates by incorporating metals and their conductive oxides Methods for forming dual-metal gate CMOS transistors are described. An NMOS and a PMOS active area of a semiconductor substrate are separated by isolation regions. A metal layer is deposited over a gate dielectric layer in each active area. Oxygen ions are implanted...	12/28/2004
6821888	Method of copper/copper surface bonding using a conducting polymer for application in IC chip bonding A semiconductor chip having an exposed metal terminating pad thereover, and a separate substrate having a corresponding exposed metal bump thereover are provided. A conducting polymer plug is formed over the exposed metal terminating pad. A conforming interface laye...	11/23/2004
6813796	Apparatus and methods to clean copper contamination on wafer edge A new apparatus is provided that can be applied to clean outer edges of semiconductor substrates. Under the first embodiment of the invention, a brush is mounted on the surface of the substrate around the periphery of the substrate, chemicals are fed to the surface ...	11/09/2004
6797605	Method to improve adhesion of dielectric films in damascene interconnects Method of improving adhesion of low dielectric constant films to other dielectric films and barrier metals in a damascene process are achieved. In one method, a low dielectric constant material layer is deposited on a substrate. Silicon ions are implanted into the l...	09/28/2004
6762085	Method of forming a high performance and low cost CMOS device A method of fabricating a CMOS device with reduced processing costs as a result of a reduction in photolithographic masking procedures, has been developed. The method features formation of L shaped silicon oxide spacers on the sides of gate structures, with a vertic...	07/13/2004
6750519	Dual metal gate process: metals and their silicides Methods for forming dual-metal gate CMOS transistors are described. An NMOS and a PMOS active area of a semiconductor substrate are separated by isolation regions. A metal layer is deposited over a gate dielectric layer in each active area. Silicon ions are implante...	06/15/2004
6730591	Method of using silicon rich carbide as a barrier material for fluorinated materials A method of forming interconnect structures in a semiconductor device, comprising the following steps. A semiconductor structure is provided. In the first embodiment, at least one metal line is formed over the semiconductor structure. A silicon-rich carbide barrier ...	05/04/2004
6720204	Method of using hydrogen plasma to pre-clean copper surfaces during Cu/Cu or Cu/metal bonding A method of bonding a wire to a metal bonding pad, comprising the following steps. A semiconductor die structure having an exposed metal bonding pad within a chamber is provided. The bonding pad has an upper surface. A hydrogen-plasma is produced within the chamber ...	04/13/2004
6705512	Method of application of conductive cap-layer in flip-chip, cob, and micro metal bonding A method of bonding a bonding element to a metal bonding pad comprises the following steps. A semiconductor structure having an exposed, recessed metal bonding pad within a layer opening is provided. The layer has an upper surface. A conductive cap having a predeter...	03/16/2004
6692579	Method for cleaning semiconductor structures using hydrocarbon and solvents in a repetitive vapor phase/liquid phase sequence A method for cleaning a semiconductor structure using vapor phase condensation with a thermally vaporized cleaning agent, a hydrocarbon vaporized by pressure variation, or a combination of the two. In the thermally vaporized cleaning agent process, a semi...	02/17/2004
6690091	Damascene structure with reduced capacitance using a boron carbon nitride passivation layer, etch stop layer, and/or cap layer A damascene structure with reduced capacitance dielectric stacking comprise a passivation, a first dielectric, an etch stop, a second dielectric and a cap layer over a first conductive layer formed on a semiconductor. The passivation, the etch stop, and t...	02/10/2004
6683002	Method to create a copper diffusion deterrent interface Method and product for forming a dual damascene interconnect structure, wherein depositing a copper sulfide interface layer as sidewalls to the opening deters migration or diffusing of copper ions into the dielectric material....	01/27/2004
6677652	Methods to form dual metal gates by incorporating metals and their conductive oxides Methods for forming dual-metal gate CMOS transistors are described. An NMOS and a PMOS active area of a semiconductor substrate are separated by isolation regions. A metal layer is deposited over a gate dielectric layer in each active area. Oxygen ions ar...	01/13/2004
6638365	Method for obtaining clean silicon surfaces for semiconductor manufacturing A method of preparing a silicon surface for a subsequent processing said such as thermal oxidation, or metal silicide formation, via use of a novel wet chemical clean procedure, has been developed. The novel wet chemical clean procedure is comprised of th...	10/28/2003
6602801	Method for forming a region of low dielectric constant nanoporous material A method for forming a region of low dielectric constant nanoporous material is disclosed. In one embodiment, the present method includes the step of combining a plurality of materials to form a solution. In the present embodiment, the plurality of materi...	08/05/2003
6566260	Non-metallic barrier formations for copper damascene type interconnects A method for forming dual-damascene type conducting interconnects with non-metallic barriers that protect said interconnects from fluorine out-diffusion from surrounding low-k, fluorinated dielectric materials. One embodiment of the method is particularly...	05/20/2003
6565664	Method for stripping copper in damascene interconnects An inexpensive and safe copper removal method in the fabrication of integrated circuits is described. Copper is stripped or removed by a chemical mixture comprising an ammonium salt, an amine, and water. The rate of copper stripping can be controlled by v...	05/20/2003
6540841	Method and apparatus for removing contaminants from the perimeter of a semiconductor substrate A new method and apparatus is provided that can be applied to clean outer edges of semiconductor substrates. Under the first embodiment of the invention, a brush is mounted on the surface of the substrate around the periphery of the substrate, chemicals a...	04/01/2003
6534388	Method to reduce variation in LDD series resistance A process used to retard out diffusion of P type dopants from P type LDD regions, resulting in unwanted LDD series resistance increases, has been developed. The process features the formation of a nitrogen containing layer, placed between the P type LDD r...	03/18/2003
6530380	Method for selective oxide etching in pre-metal deposition A method for completely removing dielectric layers formed selectively upon a substrate employed within a microelectronics fabrication from regions wherein closely spaced structures such as self-aligned metal silicide (or salicide) electrical contacts may ...	03/11/2003
6531386	Method to fabricate dish-free copper interconnects A method of fabricating at least one metal interconnect including the following steps. A structure having at least one exposed conductive structure is provided. A non-stick material layer is formed over the structure and the at least one exposed conductiv...	03/11/2003
6531390	Non-metallic barrier formations for copper damascene type interconnects A method for forming dual-damascene type conducting interconnects with non-metallic barriers that protect said interconnects from fluorine out-diffusion from surrounding low-k, fluorinated dielectric materials. One embodiment of the method is particularly...	03/11/2003
6524963	Method to improve etching of organic-based, low dielectric constant materials A method etching an organic-based, low dielectric constant material in the manufacture of an integrated circuit device has been achieved. Organic materials without silicon and organic materials without fluorine can be etched by using, for example, hydrazi...	02/25/2003
6524910	Method of forming dual thickness gate dielectric structures via use of silicon nitride layers A process for forming a first group of gate structures, designed to operate at a lower voltage than a simultaneously formed second group of gate structures, has been developed. The process features the thermal growth of a first silicon dioxide gate insula...	02/25/2003
6513374	Apparatus to quantify the adhesion of film A new apparatus is provided for the quantification of the adhesion of a film over a substrate. In particular, the peeling force and the rate of peeling are quantified by providing a first means for measuring the peeling force, a second means for measuring...	02/04/2003
6489233	Non-metallic barrier formations for copper damascene type interconnects A method for forming dual-damascene type conducting interconnects with non-metallic barriers that protect said interconnects from fluorine out-diffusion from surrounding low-k, fluorinated dielectric materials. One embodiment of the method is particularly...	12/03/2002
6486080	Method to form zirconium oxide and hafnium oxide for high dielectric constant materials A new method of forming a metal oxide high dielectric constant layer in the manufacture of an integrated circuit device has been achieved. A substrate is provided. A metal oxide layer is deposited overlying the substrate by reacting a precursor with an ox...	11/26/2002
6479383	Method for selective removal of unreacted metal after silicidation A method to remove a metal from over a substrate in the fabrication of an integrated circuit device. The invention comprises providing a metal layer over a substrate. The metal layer is exposed to a reactant gas to form at least a solid metal containing p...	11/12/2002

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Inventor: Simon Chooi