|Application No.||Application Title||Issue Date|
|20130003444||SEMICONDUCTOR MEMORY DEVICE AND TEST METHOD THEREFOR|
Provided is a semiconductor memory device including: first and second SRAM cells; a first hit line pair provided with the first SRAM cell; a second bit line pair provided with the second SRAM cell; a first switch circuit provided between the first bit line pair and the ...
|20090086529||SEMICONDUCTOR STORAGE DEVICE|
In a semiconductor storage device including a transistor for reading port, undesired voltage decrease may occur in a bit line in a reading operation due to a leak current from the transistor for reading port of a memory cell, which may cause a reading error. A semicondu...