Inventor: Robert Feurle

Address: Neubiberg, DE
No. of patents: 32
Last patent issue date: 07/18/2006

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Number	Title	Issue Date
7078133	Photolithographic mask A photolithographic mask has the advantage that a combination of dummy structures, whose pattern is imaged into the resist layer, and auxiliary structures, whose pattern is not imaged into the resist layer, makes it possible to achieve a significant improvement in t...	07/18/2006
6922764	Memory, processor system and method for performing write operations on a memory region A memory is provided which has a memory region for storing data, an input for receiving a data bundle with a plurality of temporally sequential data blocks and an input for receiving a data mask signal which is assigned to the data bundle. The memory also has a unit...	07/26/2005
6894379	Sharing of multiple-access signal line in a printed circuit board A printed circuit board system includes a printed circuit board device having a multiple access signal line. A plurality of semiconductor apparatuses are arranged on the printed circuit board device. Each semiconductor apparatus includes a signal connection point to...	05/17/2005
6816432	Integrated semiconductor circuit having transistors that are switched with different frequencies It is known to adapt the dimensions of transistors, in particular a layer thickness of a local gate oxide in a manner dependent on an operating voltage. Therefore, semiconductor circuits having transistors with different operating voltages are provided with transist...	11/09/2004
6781220	Printed circuit board for semiconductor memory device In a semiconductor memory device, a printed circuit board connects a memory chip to an external circuit. The printed circuit board includes a multiplicity of pads arranged in a column. These pads connect the board to the memory chip. The board also includes a multip...	08/24/2004
6768693	Integrated dynamic memory with control circuit for controlling a refresh mode of memory cells, and method for driving the memory An integrated dynamic memory contains a control circuit for controlling a refresh mode in which the memory cells undergo refreshing of their contents. A controllable frequency generator serves for setting a refresh frequency. A temperature sensor circuit detects a t...	07/27/2004
6751145	Volatile semiconductor memory and mobile device The volatile semiconductor memory is constructed from a plurality of memory segments. The information stored in the memory cells must be regularly reconditioned. Here, the time interval after the expiry of which the memory contents of the memory cells are reconditio...	06/15/2004
6728143	Integrated memory An integrated memory having a memory cell array has a control circuit for controlling a memory access for reading out or writing a data signal of one of the memory cells. The control circuit receives, for a memory access, an access command in the form of an activati...	04/27/2004
6707705	Integrated dynamic memory device and method for operating an integrated dynamic memory In order to operate an integrated dynamic memory having a memory cell array having bit lines and word lines a plurality of individual actions—to be performed for a memory access—from the activation of one of the word lines up to the precharging of the word lines...	03/16/2004
6700831	Integrated memory having a plurality of memory cell arrays and method for operating the integrated memory An integrated memory has a plurality of memory cell arrays. The memory cell arrays are in each case assigned a decoder for selecting bit lines and word lines. In order to trigger an access cycle for a memory cell access, a write command or a read command ...	03/02/2004
6646908	Integrated memory chip with a dynamic memory The integrated memory chip has an external control terminal, a dynamic memory, and a control circuit for controlling a memory access to the dynamic memory. The control circuit is connected to the external control terminal, for receiving an access command ...	11/11/2003
6643211	Integrated memory having a plurality of memory cell arrays What is specified is an integrated memory having a plurality of memory cell arrays that are each assigned row decoders and column decoders. During read or write operations in the present integrated memory, in each case at least two word lines are activate...	11/04/2003
6639825	Data memory The data memory device has a plurality of memory cells for storing data which are represented by a first physical value of the storing memory elements, especially their conductivity or charge. The memory elements are, for example, storage capacitors. A de...	10/28/2003
6628553	Data output interface, in particular for semiconductor memories A data output interface, in particular for semiconductor memories, provides a plurality of output drivers for providing data output signals in a manner dependent on a read command and a clock signal. In order to signal to a microprocessor that can be conn...	09/30/2003
6614706	Voltage regulating circuit, in particular for semiconductor memories The voltage regulating circuit, in particular for semiconductor memories, has a reference-voltage generator for generating a reference voltage, an in-phase element for providing a regulated voltage, and an error amplifier for forming a control loop. The i...	09/02/2003
6615289	Semiconductor chip configuration and method of controlling a semiconductor chip An integrated semiconductor chip is connected to external terminals with all of its data-carrying bonding pads. One of a plurality of possible data input/data output organizational forms is preset for a normal mode. Not all of the data-carrying bonding pa...	09/02/2003
6528392	Dicing configuration for separating a semiconductor component from a semiconductor wafer The dicing configuration for separating a semiconductor component from a semiconductor wafer is formed with a rupture joint which is created together with connecting holes that interconnect metallization planes, in a transition area between a scribe line ...	03/04/2003
6492729	Configuration and method for connecting conductor tracks A configuration for connecting conductor tracks includes a first conductor track fabricated with a first phase mask having a first phase and a second conductor track fabricated with a second phase mask having a second phase opposite to the first phase. Th...	12/10/2002
6480039	Input buffer of an integrated semiconductor circuit An integrated semiconductor circuit having a first operating mode and a second operating mode has a plurality of input buffers. At least one of the input buffers serves for controlling a changeover between the operating modes. The input buffer for control...	11/12/2002
6456522	Integrated memory having memory cells and buffer capacitors An integrated memory includes memory cells each having a selector transistor and a storage capacitor. In each memory cell, the storage capacitor is connected to one of a plurality of column lines through the selector transistor, and a control terminal of ...	09/24/2002
6441469	Semiconductor memory configuration with dummy components on continuous diffusion regions The semiconductor memory configuration has at least two memory cell arrays. The open area between the strips of the sense-amp transistors in the two memory cell arrays contains dummy transistors. This avoids proximity effects at the edges of the sense-amp...	08/27/2002
6433617	Configuration for reducing the number of measuring pads on a semiconductor chip The invention relates to a configuration for reducing the number of pads on a semiconductor chip (1) with an integrated circuit. This configuration includes an analog/digital converter (3), which feeds internal voltages that are delivered by different loc...	08/13/2002
6426899	Integrated memory with a buffer circuit An integrated memory includes two potential nodes at which a supply voltage is present. Memory cells each have a selection transistor and a storage capacitor. At least one series circuit is disposed between the two potential nodes. The series circuits eac...	07/30/2002
6317378	Buffer circuit A buffer circuit serves for buffering a supply voltage of an integrated circuit. The supply voltage is present between two potential nodes. A series circuit is disposed between the two potential nodes and includes at least two buffer capacitors between wh...	11/13/2001
6317374	Method for operating a current sense amplifier A method for operating a current sense amplifier having a latch configuration improves the signal-to-noise ratio by setting the supply voltage for the latch configuration to be greater than a voltage which is present at the input of the current sense ampl...	11/13/2001
6310399	Semiconductor memory configuration with a bit-line twist A semiconductor memory configuration includes bit lines in a bit-line plane, a further plane different from the bit-line plane, word lines, and a memory cell area adjacent the bit-line plane, some of the bit lines having a twist running alongside others o...	10/30/2001
6302729	Integrated circuit with electrical connection points that can be severed by the action of energy An integrated circuit includes electrical conductor tracks adjacently disposed parallel to one another and running substantially in a first direction. The tracks have at least three electrical connection points that can be severed by energy. The connectio...	10/16/2001
6294841	Integrated semiconductor circuit having dummy structures An integrated semiconductor circuit includes dummy structures. A portion of capacitive elements present in the dummy structures is used in order to adapt input/output parameters of pads of the integrated semiconductor circuit to an external line. Metal op...	09/25/2001
6281586	Integrated semiconductor circuit configuration having stabilized conductor tracks An integrated semiconductor circuit configuration includes stabilized conductor tracks which run in different planes. Critical locations of the conductor tracks which are dictated by the layout are provided with dummy contacts....	08/28/2001
6240005	Sense amplifier configuration with fused diffusion regions and a distributed driver system The sense-amp transistors of the sense amplifier configuration are arranged in a common continuous diffusion region. The drivers are disposed directly adjacent and parallel to the diffusion region. A short local connection between the sense-amp transistor...	05/29/2001
6236612	Integrated semiconductor memory configuration with self-buffering of supply voltages The integrated semiconductor memory configuration has a plurality of memory cell fields connected to one another by low-resistance supply lines forming a power network. The power network is connected to a voltage generator via a high-resistance supply lin...	05/22/2001
6205044	Decoder connection configuration for memory chips with long bit lines A decoder connection configuration for memory chips, in which, in a dummy region of a decoder, the dummy region being caused by a bit line twist, additional plated-through holes are provided between power supply lines and the decoder. By virtue of the bit...	03/20/2001

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Inventor: Robert Feurle