|7720294||Unified decoder architecture|
Presented herein is a unified decoder architecture. A system comprises a video decoder, instruction memory, and a host processor. The video decoder decodes the video data encoded with the particular standard. The instruction memory stores a first set of instructions...
|7284072||DMA engine for fetching words in reverse order|
Presented herein is a direct memory access engine for providing data words in the reverse order. The data words are fetched in batches comprising a predetermined number of data words starting from the last data word and proceeding to the first data word. The batches...