Inventor: Rajesh Khamankar

Address: Coppell, TX
No. of patents: 32
Last patent issue date: 02/14/2012

Number	Title	Issue Date
8114784	Laminated stress overlayer using In-situ multiple plasma treatments for transistor improvement Integrated circuits (ICs) commonly contain pre-metal dielectric (PMD) liners with compressive stress to increase electron and hole mobilities in MOS transistors. The increase is limited by the thickness of the PMD liner. The instant invention is a multi-layered PMD ...	02/14/2012
8084787	PMD liner nitride films and fabrication methods for improved NMOS performance Semiconductor devices (102) and fabrication methods (10) are provided, in which a nitride film (130) is formed over NMOS transistors to impart a tensile stress in ail or a portion of the NMOS transistor to improve carrier mobility. The nitride l...	12/27/2011
8084312	Nitrogen based implants for defect reduction in strained silicon A transistor is fabricated upon a semiconductor substrate, where the yield strength or elasticity of the substrate is enhanced or otherwise adapted. A strain inducing layer is formed over the transistor to apply a strain thereto to alter transistor operating charact...	12/27/2011
8021990	Gate structure and method A MOSFET structure including silicate gate dielectrics with nitridation treatments of the gate dielectric prior to gate material deposition. ...	09/20/2011
7847401	Methods, systems and structures for forming semiconductor structures incorporating high-temperature processing steps A method (100) of forming semiconductor structures (202) including high-temperature processing steps (step 118), incorporates the use of a high-temperature nitride-oxide mask (220) over protected regions (214) of the device (202...	12/07/2010
7682988	Thermal treatment of nitrided oxide to improve negative bias thermal instability A method of reducing threshold voltage shift of a MOSFET transistor resulting after temperature and voltage stress, and an integrated circuit device fabricated according to the method. The method includes the steps of forming a nitrided dielectric layer on a semicon...	03/23/2010
7670892	Nitrogen based implants for defect reduction in strained silicon A transistor is fabricated upon a semiconductor substrate, where the yield strength or elasticity of the substrate is enhanced or otherwise adapted. A strain inducing layer is formed over the transistor to apply a strain thereto to alter transistor operating charact...	03/02/2010
7601575	Integration of pre-S/D anneal selective nitride/oxide composite cap for improving transistor performance The present invention facilitates semiconductor device operation and fabrication by providing a cap-annealing process that improves channel electron mobility without substantially degrading PMOS transistor devices. The process uses an oxide/nitride composite cap to ...	10/13/2009
7560792	Reliable high voltage gate dielectric layers using a dual nitridation process Dual gate dielectric layers are formed on a semiconductor substrate for MOS transistor fabrication. A first dielectric layer (30) is formed on a semiconductor substrate (10). A first plasma nitridation process is performed on said first dielectric laye...	07/14/2009
7553718	Methods, systems and structures for forming semiconductor structures incorporating high-temperature processing steps A method (100) of forming semiconductor structures (202) including high-temperature processing steps (step 118), incorporates the use of a high-temperature nitride-oxide mask (220) over protected regions (214) of the device (202...	06/30/2009
7535066	Gate structure and method A MOSFET structure including silicate gate dielectrics with nitridation treatments of the gate dielectric prior to gate material deposition. ...	05/19/2009
7514308	CMOS device having different amounts of nitrogen in the NMOS gate dielectric layers and PMOS gate dielectric layers The present invention provides a complementary metal oxide semiconductor (CMOS) device, a method of manufacture therefor, and an integrated circuit including the same. The CMOS device (100), in an exemplary embodiment of the present invention, includes a p-ch...	04/07/2009
7402524	Post high voltage gate oxide pattern high-vacuum outgas surface treatment The present invention provides a method for fabricating a dual gate semiconductor device. In one aspect, the method comprises forming a nitridated, high voltage gate dielectric layer over a semiconductor substrate, patterning a photoresist over the nitridated, high ...	07/22/2008
7345001	Gate dielectric having a flat nitrogen profile and method of manufacture therefor The present invention provides a gate dielectric having a flat nitrogen profile, a method of manufacture therefor, and a method of manufacturing an integrated circuit including the flat nitrogen profile. In one embodiment, the method of manufacturing the gate dielec...	03/18/2008
7339240	Dual-gate integrated circuit semiconductor device The present invention provides a method for fabricating a dual gate semiconductor device. In one aspect, the method comprises forming a nitridated, high voltage gate dielectric layer over a semiconductor substrate, patterning a photoresist over the nitridated, high ...	03/04/2008
7226834	PMD liner nitride films and fabrication methods for improved NMOS performance Semiconductor devices (102) and fabrication methods (10) are provided, in which a nitride film (130) is formed over NMOS transistors to impart a tensile stress in all or a portion of the NMOS transistor to improve carrier mobility. The nitride l...	06/05/2007
7227201	CMOS device having different amounts of nitrogen in the NMOS gate dielectric layers and PMOS gate dielectric layers The present invention provides a complementary metal oxide semiconductor (CMOS) device, a method of manufacture therefor, and an integrated circuit including the same. The CMOS device (100), in an exemplary embodiment of the present invention, includes a p-ch...	06/05/2007
7217626	Transistor fabrication methods using dual sidewall spacers Methods (50) are presented for transistor fabrication, in which first and second sidewall spacers (120a, 120b) are formed laterally outward from a gate structure (114), after which a source/drain region (116) is impla...	05/15/2007
7192894	High performance CMOS transistors using PMD liner stress A silicon nitride layer (110) is formed over a transistor gate (40) and source and drain regions (70). The as-formed silicon nitride layer (110) comprises a first tensile stress and a high hydrogen concentration. The as-formed silicon nit...	03/20/2007
7183165	Reliable high voltage gate dielectric layers using a dual nitridation process Dual gate dielectric layers are formed on a semiconductor substrate for MOS transistor fabrication. A first dielectric layer (30) is formed on a semiconductor substrate (10). A first plasma nitridation process is performed on said first dielectric laye...	02/27/2007
7129127	Integration scheme to improve NMOS with poly cap while mitigating PMOS degradation A method (200) fabricating a semiconductor device is disclosed. A poly oxide layer is formed over gate electrodes (210) on a semiconductor body and active regions defined within the semiconductor body in PMOS and NMOS regions. A nitride containing cap ...	10/31/2006
7049242	Post high voltage gate dielectric pattern plasma surface treatment The present invention provides a method for fabricating a dual gate semiconductor device. In one aspect, the method comprises forming a nitridated, high voltage gate dielectric layer over a semiconductor substrate, patterning a photoresist over the nitridated, high ...	05/23/2006
7018925	Post high voltage gate oxide pattern high-vacuum outgas surface treatment The present invention provides a method for fabricating a dual gate semiconductor device. In one aspect, the method comprises forming a nitridated, high voltage gate dielectric layer over a semiconductor substrate, patterning a photoresist over the nitridated, high ...	03/28/2006
7012028	Transistor fabrication methods using reduced width sidewall spacers Transistor fabrication methods (50) are presented in which shrinkable sidewall spacers (120) are formed (66, 68) along sides of a transistor gate (114), and a source/drain implant is performed (74) after forming the sidewall spacer...	03/14/2006
6930007	Integration of pre-S/D anneal selective nitride/oxide composite cap for improving transistor performance The present invention facilitates semiconductor device operation and fabrication by providing a cap-annealing process that improves channel electron mobility without substantially degrading PMOS transistor devices. The process uses an oxide/nitride composite-cap to ...	08/16/2005
6869862	Method for improving a physical property defect value of a gate dielectric The present invention provides a method for improving a physical property of a substrate, a method for manufacturing an integrated circuit, and an integrated circuit manufactured using the aforementioned method. In one aspect of the invention, the method for improvi...	03/22/2005
6780719	Method for annealing ultra-thin, high quality gate oxide layers using oxidizer/hydrogen mixtures An embodiment of the present invention is a method of forming an ultra-thin dielectric layer, the method comprising the steps of: providing a substrate having a semiconductor surface; forming an oxygen-containing layer on the semiconductor surface; exposing the oxyg...	08/24/2004
6730566	Method for non-thermally nitrided gate formation for high voltage devices A method is provided for non-thermally nitrided gate formation of high voltage transistor devices. The non-thermally nitrided gate formation is useful in the formation of dual thickness gate dielectric structures. The non-thermally nitrided gate formation comprises ...	05/04/2004
6632747	Method of ammonia annealing of ultra-thin silicon dioxide layers for uniform nitrogen profile An embodiment of the present invention is a method of forming an ultra-thin dielectric layer by providing a substrate having a semiconductor surface; forming an oxygen-containing layer on the semiconductor surface; exposing the oxygen-containing layer to ...	10/14/2003
6610614	Method for uniform nitridization of ultra-thin silicon dioxide layers in transistor gates A method of forming an ultra-thin dielectric layer, including the steps of: providing a substrate having a semiconductor surface; forming an oxygen-containing layer on the semiconductor surface; exposing the oxygen-containing layer to a nitrogen-containin...	08/26/2003
6548366	Method of two-step annealing of ultra-thin silicon dioxide layers for uniform nitrogen profile An embodiment of the present invention is a method of forming an ultra-thin dielectric layer, the method comprising the steps of: providing a substrate having a semiconductor surface; forming an oxygen-containing layer on the semiconductor surface; exposi...	04/15/2003
6503846	Temperature spike for uniform nitridization of ultra-thin silicon dioxide layers in transistor gates An embodiment of the present invention is a method of forming an ultra-thin dielectric layer, the method comprising the steps of: providing a substrate having a semiconductor surface; forming an oxygen-containing layer on the semiconductor surface; exposi...	01/07/2003

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Inventor: Rajesh Khamankar