Inventor: Prashant U. Kenkare

Address: Austin, TX
No. of patents: 29
Last patent issue date: 11/20/2012

Number	Title	Issue Date
8315117	Integrated circuit memory having assisted access and method therefor A memory and method for access the memory are provided. A first test is used to test memory elements to determine a lowest power supply voltage at which all the memory elements will operate to determine a weak memory element. Redundancy is used to substitute a redun...	11/20/2012
8156357	Voltage-based memory size scaling in a data processing system A memory has bits that fail as power supply voltage is reduced to reduce power and/or increase endurance. The bits become properly functional when the power supply voltage is increased back to its original value. With the reduced voltage, portions of the memory that...	04/10/2012
8143929	Flip-flop having shared feedback and method of operation A method of operating a circuit includes receiving a first data signal at a first node. The first node is coupled to a second node to couple the first data signal to the second node. After coupling the first node to the second node, the second node is coupled to a t...	03/27/2012
8120975	Memory having negative voltage write assist circuit and method therefor A method of writing data to a selected column of a memory includes selecting a first column. The data writing is initiated by applying a logic high to a first bit line of the first column and a first potential to a second bit line of the first column that is lower t...	02/21/2012
8059482	Memory using multiple supply voltages A memory has a method of operating that includes performing operations of a first type and a second type. A first voltage is coupled to a power supply node of a first memory cell of a memory array during a first operation of the first type. The first voltage is deco...	11/15/2011
8031549	Integrated circuit having boosted array voltage and method therefor An integrated circuit comprises a global power supply conductor, a plurality of circuit blocks, a plurality of voltage converters, and control logic. The global power supply conductor is configured to distribute a supply voltage. The circuit blocks are selectively c...	10/04/2011
8009489	Memory with read cycle write back A memory has a first bit line, a second bit line, and a word line. A memory cell is coupled to the word line and the first and second bit lines. A sense amplifier has a first input, a second input, a first output, and a second output. A pair of coupling transistors ...	08/30/2011
8004907	SRAM with read and write assist A memory includes an SRAM bitcell including a pair of cross-coupled inverters, wherein a first inverter of the pair includes a first device having a body and a second inverter of the pair includes a second device having a body. A first selection circuit has a first ...	08/23/2011
7984229	Pipelined tag and information array access with speculative retrieval of tag that corresponds to information access A cache design is described in which corresponding accesses to tag and information arrays are phased in time, and in which tags are retrieved (typically speculatively) from a tag array without benefit of an effective address calculation subsequently used for a corre...	07/19/2011
7870400	System having a memory voltage controller which varies an operating voltage of a memory and method therefor A system and method saves power in a system memory of a processing system. A peripheral, a processor, an arbiter and a system memory are coupled to a system communication bus for communicating via the system communication bus. In one form a voltage controller is cou...	01/11/2011
7843218	Data latch with structural hold A multiplexed data flip-flop circuit (500) is described in which a multiplexer (510) outputs functional or scan data, a master latch (520) generates a master latch output signal at a hold time under control of a master clock signal, a slave latc...	11/30/2010
7671629	Single-supply, single-ended level conversion circuit for an integrated circuit having multiple power supply domains A circuit comprises first, second, third, and fourth transistors. The first transistor has a first current electrode, a control electrode for receiving an input signal, and a second current electrode. The second transistor has a first current electrode coupled to th...	03/02/2010
7630272	Multiple port memory with prioritized world line driver and method thereof A multiple port memory has a word line driver that provides a word line signal to access a first write port of a multiple port memory cell in an array of multiple port memory cells during a write operation. A first logic circuit has a first input for receiving a fir...	12/08/2009
7623404	Memory device having concurrent write and read cycles and method thereof A memory device includes a latch having an input to receive a bit value, an input to receive a clock signal, and an output to provide a latched bit value based on the clock signal. The memory device further includes a bit cell including a storage component, and a wr...	11/24/2009
7573762	One time programmable element system in an integrated circuit A system with a repairable memory array having redundant memory cells to replace one or more defective memory cells that are detected after fabrication. The system also includes non memory array circuits having circuitry that may adjust one or more operating paramet...	08/11/2009
7548102	Data latch with minimal setup time and launch delay The present invention provides a latch circuit that is operable to generate a pulse from first and second clock signals to allow gates in a datapath to propagate data with minimal latency. The first clock signal is a version of the system clock and the second contro...	06/16/2009
7542369	Integrated circuit having a memory with low voltage read/write operation An integrated circuit with a low voltage read/write operation is provided. The integrated circuit may include a processor and a plurality of memory cells organized in rows and columns and coupled to the processor, wherein a row of memory cells comprises a word line ...	06/02/2009
7492627	Memory with increased write margin bitcells A memory comprising a first bit line, a second bit line, a word line, a first pair of cross-coupled inverters having a first input/output node and a second input/output node, a first power supply node and a second power supply node, wherein the first power supply no...	02/17/2009
7489540	Bitcell with variable-conductance transfer gate and method thereof A memory device comprises a bit cell comprising a bit storage device, a first word line, a second word line, and a first transfer gate to connect the bit storage device to a bit line. The first transfer gate is configurable to at least four conductance states based ...	02/10/2009
7369452	Programmable cell A device having an OTP memory is disclosed. A program state of the OTP device is stored at a fuse that is connected in series between a first node and a latch. During a program mode, the first node is electrically connected to a program voltage. During a read mode, ...	05/06/2008
7365587	Contention-free keeper circuit and a method for contention elimination A contention-free keeper circuit including a keeper circuit having a first node and a second node, is provided. The contention-free keeper circuit may further include a delay element for providing time delay. The contention-free keeper circuit may further include a ...	04/29/2008
7362134	Circuit and method for latch bypass A device includes a first combinatorial logic stage having a first input to receive a first data value, a second input to receive a bypass value and an output to provide one of a representation of the first data value or a first predetermined value based on the bypa...	04/22/2008
7349266	Memory device with a data hold latch A memory device includes a plurality of pairs of complimentary bit lines and a plurality of latch circuits. Each pair of the plurality of pairs of complimentary bit lines is coupled to a column of memory cells. Each latch circuit has an input coupled to a data line ...	03/25/2008
7295487	Storage circuit and method therefor Storage circuits (180-183 and 280-281) may be used for low power operation while allowing fast read access. In one embodiment (e.g. circuit 100), shared complementary write bit lines (101, 102), separate read bit lines (1...	11/13/2007
7292495	Integrated circuit having a memory with low voltage read/write operation An integrated circuit with a low voltage read/write operation is provided. The integrated circuit may include a processor and a plurality of memory cells organized in rows and columns and coupled to the processor, wherein a row of memory cells comprises a word line ...	11/06/2007
7242626	Method and apparatus for low voltage write in a static random access memory An integrated circuit memory includes a plurality of memory cells, where each of the plurality of memory cells comprises a first storage node and a second storage node. Each of the plurality of memory cells comprises a transistor coupled between the first and second...	07/10/2007
7200020	Storage element with clear operation and method thereof A storage device and a method in the storage element, where the storage element has a first data storage node and a second data storage node and where the first data storage node is coupled to a bit line via a first pass transistor and where the second data storage ...	04/03/2007
7193924	Dual-port static random access memory having improved cell stability and write margin A dual-port memory includes a plurality of memory cells coupled to a row decoder and column logic. Each memory cell includes two storage nodes, where each storage node is coupled to a bit line via an access transistor. Each memory cell also includes a logic gate for...	03/20/2007
7161827	SRAM having improved cell stability and method therefor A SRAM (14) includes a SRAM cell (26), the cell (26) includes a first storage node (N1), a second storage node (N2), and a cross coupled latch (40) including a first primary source current path to the first storage node, a f...	01/09/2007

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Inventor: Prashant U. Kenkare