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Inventor: Peter Wright


Address: Sunnyvale, CA
No. of patents: 2
Last patent issue date: 06/29/1999

NumberTitleIssue Date
5915756Method to fill via holes between two conductive layers
A method of filling via holes between a lower conductive layer and an upper conductive layer whereby the hole is filled by the lower conductive layer. By optimizing conditions such as compressive stress and temperature during the deposition of the various...
06/29/1999
5523247Method of fabricating self-aligned planarized well structures
A method of forming a planarized self-aligned integrated circuit structure suitable for forming CMOS circuitry is provided. The method involves using first and second barrier layers to define the dopant regions for first and second wells, respectively. Th...
06/04/1996
 
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