Inventor: Michael W. Williams

Address: Citrus Heights, CA
No. of patents: 34
Last patent issue date: 08/25/2009

Number	Title	Issue Date
7580465	Low speed access to DRAM Embodiments provide access to a memory over a high speed serial link at slower speeds than the high speed serial links regular operation. An embodiment may comprise a memory apparatus with a differential receiver coupled to a protocol recognition circuit, a low spee...	08/25/2009
7353329	Memory buffer device integrating refresh logic Apparatus and method to carry out refresh operations on rows of memory cells within a memory device independently of a memory controller during times when there is no activity on a memory bus coupling the memory device to the memory controller that involves the memo...	04/01/2008
7243205	Buffered memory module with implicit to explicit memory command expansion Method and apparatus for use with buffered memory modules are included among the embodiments. In exemplary systems, the memory module has a buffer that receives memory commands and data, and then presents those commands and data to physical memory devices through a ...	07/10/2007
6976121	Apparatus and method to track command signal occurrence for DRAM data transfer An apparatus and a method to track command signal occurrence for DRAM data transfer have been disclosed. In one embodiment, the apparatus includes an interface to couple to a data bus, the data bus to transfer data between the interface and one or more memory device...	12/13/2005
6976120	Apparatus and method to track flag transitions for DRAM data transfer A method and an apparatus to track transition of a flag signal for DRAM data transfer have been disclosed. In one embodiment, the apparatus includes one or more memory devices, coupled to a data bus, to receive a command signal, wherein the command signal initiates ...	12/13/2005
6957307	Mapping data masks in hardware by controller programming A memory controller or other device may be programmed with a data mask mapping scheme. A selection device within the memory controller may be set with the data mask mapping scheme between data and a data mask. In one embodiment, a storage device may be included and ...	10/18/2005
6952367	Obtaining data mask mapping information A data mask map may be programmed into a storage device in various ways. In one embodiment, the data mask is hardwired into a selection device to reorder either the data mask bits or the data chunks. In another embodiment, a data mask map is retrieved from a locatio...	10/04/2005
6941484	Synthesis of a synchronization clock A method, system, and device capable of generating one or more clocks internally to detect, sample, and receive synchronous data streams and eliminate the need for corresponding external synchronization clocks for each data stream. One aspect of the clock generator ...	09/06/2005
6928494	Method and apparatus for timing-dependant transfers using FIFOs A method and apparatus for communicating commands and/or data between two different time domains. In one embodiment, multiple memory commands are placed into one or more FIFOs in a manner that specifies the delays that must take place between execution of the differ...	08/09/2005
6925013	Obtaining data mask mapping information A data mask map may be programmed into a storage device in various ways. In one embodiment, the data mask is hardwired into a selection device to reorder either the data mask bits or the data chunks. In another embodiment, a data mask map is retrieved from a locatio...	08/02/2005
6915399	Cross-clock domain data transfer method and apparatus An apparatus and method for transferring units of information between clock domains. A respective set of N units of information is loaded from an output circuit in a first clock domain into a storage circuit in a second clock domain during each cycle of the first cl...	07/05/2005
6862653	System and method for controlling data flow direction in a memory system A system and method for controlling the direction of data flow in a memory system is provided. The system comprising memory devices, a memory controller, a buffering structure, and a data flow director. The memory controller sends data, such as read-data, write-data...	03/01/2005
6829184	Apparatus and method for encoding auto-precharge A technique to encode a precharge command on a flag signal used to execute data transfer to and from a DRAM. ...	12/07/2004
6772352	Method and apparatus for reducing the rate of commands being issued if the rate exceeds a threshold which is based upon a temperature curve A method of issuing activate commands to a memory device includes issuing the activate commands to the memory device. A number of activate commands issued within a time period is counted. A determination is made as to whether the number of activate commands issued w...	08/03/2004
6618791	System and method for controlling power states of a memory device via detection of a chip select signal A memory system and a method for controlling power states of a memory device, or a portion thereof, are provided. The memory system includes memory devices, such as DRAMs, a memory controller, chip select lines, and logic for detecting chip select signals...	09/09/2003
6604179	Reading a FIFO in dual clock domains A first-in first-out buffer (FIFO) with multiple outputs. The FIFO has an input for writing data into the FIFO. The FIFO has multiple outputs for reading the data out of the FIFO. Each output is independent from the other outputs, and can be used to read ...	08/05/2003
6553450	Buffer to multiply memory interface Providing electrical isolation between the chipset and the memory data is disclosed. The disclosure includes providing at least one buffer in a memory interface between a chipset and memory modules. Each memory module includes a plurality of memory ranks....	04/22/2003
6553449	System and method for providing concurrent row and column commands A system and method for providing concurrent column and row operations in a memory system is provided. The memory system includes a memory controller, a plurality of memory devices, and communication paths between the memory controller and the plurality o...	04/22/2003
6507530	Weighted throttling mechanism with rank based throttling for a memory system A memory system includes a plurality of memory device ranks. A memory controller having a connection with the plurality of memory device ranks is adapted to obtain command information being issued to one of the plurality of memory device ranks. The memory...	01/14/2003
6463001	Circuit and method for merging refresh and access operations for a memory device A memory controller to generate refresh requests for by storing the status of memory rows and an arithmetic logic unit to store a second status of all the memory rows of all the memory devices in the system memory configuration. A second logic unit stores...	10/08/2002
6449213	Memory interface having source-synchronous command/address signaling A memory interface scheme reduces propagation delay by utilizing source-synchronous signaling to transmit address/command information to memory devices. A memory module in accordance with the present invention may include an address/command buffer that sa...	09/10/2002
6400631	Circuit, system and method for executing a refresh in an active memory bank A memory containing a plurality of memory banks and a plurality of sense amplifiers. Also, the memory device contains a multiplexer and logic. The logic receives a refresh request for one of the plurality of memory banks and instructs the multiplexer to s...	06/04/2002
6385094	Method and apparatus for achieving efficient memory subsystem write-to-read turnaround through read posting A method of operating a memory device includes determining whether a read command is to be issued after a write command. A posted read command is issued before issuance of the write command. The posted read command is issued in place of the read command t...	05/07/2002
6370624	Configurable page closing method and apparatus for multi-port host bridges A page closing method and apparatus for multi-port host bridges. According to a method disclosed, a plurality of memory access commands are received from a plurality of command ports. A command is selected from one of the command ports to be the next memo...	04/09/2002
6252821	Method and apparatus for memory address decode in memory subsystems supporting a large number of memory devices One embodiment of the invention is a method for decoding a memory access address. A portion of the memory access address is compared to a plurality of boundary values, each of the plurality of boundary values representing an uppermost address for a group ...	06/26/2001
6226730	Achieving page hit memory cycles on a virtual address reference An apparatus and method for accessing a memory. A source address that includes a page address and a page offset is received. The page address requires translation in order to form a first address that can be used to transfer data from a row of memory cell...	05/01/2001
6212611	Method and apparatus for providing a pipelined memory controller A pipelined memory controller that includes a decode stage, and a schedule stage, wherein the schedule stage includes a command queue to store multiple commands. In one embodiment, the schedule stage further includes look ahead logic which can modify an o...	04/03/2001
6199151	Apparatus and method for storing a device row indicator for use in a subsequent page-miss memory cycle An apparatus and method for selecting a row of memory devices. A row value that indicates one of a plurality of chip select signals is stored in a storage element that is associated with a first address. A memory access request is received that includes t...	03/06/2001
6199145	Configurable page closing method and apparatus for multi-port host bridges A page closing method and apparatus for multi-port host bridges. According to a method disclosed, a plurality of memory access commands are received from a plurality of command ports. A command is selected from one of the command ports to be the next memo...	03/06/2001
6154825	Method and apparatus for addressing a memory resource comprising memory devices having multiple configurations A method and apparatus for accessing a memory resource, such as an array of DRAM modules, is described. The methodology commences with the receipt of a memory address during a memory access cycle. A row address is then generated by selecting predetermined...	11/28/2000
6128749	Cross-clock domain data transfer method and apparatus An apparatus and method for transferring units of information between clock domains. A respective set of N units of information is loaded from an output circuit in a first clock domain into a storage circuit in a second clock domain during each cycle of t...	10/03/2000
6112306	Self-synchronizing method and apparatus for exiting dynamic random access memory from a low power state A self-synchronizing method and apparatus for exiting a dynamic random access memory from a low power state is provided. The exit from the low power state is initiated. After the expiration of an exit delay period, a first quiet time is sent on a column-a...	08/29/2000
6038673	Computer system with power management scheme for DRAM devices A computer system employs DRAM devices in a memory sub-system, which devices are assigned into particular pools corresponding to different power consumption states with a most-recently-accessed (MRA) device being assigned to an active pool and placed at t...	03/14/2000
5860128	Method and apparatus for sampling data from a memory A novel method for performing memory accesses. Falling edges of a column address strobe (CAS) signal are used to cause dynamic random access memories (DRAMs) to drive data corresponding to the current address onto a data bus coupled to the input of a set ...	01/12/1999

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Inventor: Michael W. Williams