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| Number | Title | Issue Date |
| 6979878 | Isolation structure having implanted silicon atoms at the top corner of the isolation trench filling vacancies and interstitial sites A method for isolating a first active region from a second active region, both of which are configured within a semiconductor substrate. The method comprises forming a dielectric masking layer above a semiconductor substrate. An opening is then formed through the ma... | 12/27/2005 |
| 6911707 | Ultrathin high-K gate dielectric with favorable interface properties for improved semiconductor device performance An ultrathin gate dielectric having a graded dielectric constant and a method for forming the same are provided. The gate dielectric is believed to allow enhanced performance of semiconductor devices including transistors and dual-gate memory cells. A thin nitrogen-... | 06/28/2005 |
| 6767794 | Method of making ultra thin oxide formation using selective etchback technique integrated with thin nitride layer for high performance MOSFET A semiconductor device having gate oxide with a first thickness and a second thickness is formed by initially implanting a portion of the gate area of the semiconductor substrate with nitrogen ions and then forming a gate oxide on the gate area. Preferably the gate ... | 07/27/2004 |
| 6743688 | High performance MOSFET with modulated channel gate thickness A semiconductor device having gate oxide with a first thickness and a second thickness is formed by initially implanting a portion of the gate area of the semiconductor substrate with nitrogen ions and then forming a gate oxide on the gate area. Preferably the gate ... | 06/01/2004 |
| 6727569 | Method of making enhanced trench oxide with low temperature nitrogen integration A structure and an improved isolation trench between active regions within the semiconductor substrate involves forming on a silicon substrate and forming a nitride layer on the pad layer. Thereafter, a photoresist layer is patterned on the silicon nitride layer suc... | 04/27/2004 |
| 6674135 | Semiconductor structure having elevated salicided source/drain regions and metal gate electrode on nitride/oxide dielectric A semiconductor structure an a process for its manufacture. First and second gate dielectric layers are formed on a semiconductor substrate between nitride spacers, and a metal gate electrode is formed on the gate dielectric layers. Lightly-doped drain re... | 01/06/2004 |
| 6661057 | Tri-level segmented control transistor and fabrication method A transistor is formed in an active area having a segmented gate structure. The segmented gate structure advantageously provides for dynamic control of a channel region formed within the transistor. Lightly doped source and drain (LDD) regions are formed ... | 12/09/2003 |
| 6661061 | Integrated circuit with differing gate oxide thickness A semiconductor process for producing two gate oxide thicknesses within an integrated circuit in which a semiconductor substrate having a first region and a second region is provided. The first region and the second region are laterally displaced with res... | 12/09/2003 |
| 6638829 | Semiconductor structure having a metal gate electrode and elevated salicided source/drain regions and a method for manufacture A semiconductor structure and a process for its manufacture. A metal gate electrode is formed on a semiconductor substrate, the gate electrode being between nitride spacers. Lightly-doped drain regions and source/drain regions are disposed in the substrat... | 10/28/2003 |
| 6552776 | Photolithographic system including light filter that compensates for lens error A photolithographic system including a light filter that varies light intensity according to measured dimensional data that characterizes a lens error is disclosed. The light filter compensates for the lens error by reducing the light intensity of the ima... | 04/22/2003 |
| 6531364 | Advanced fabrication technique to form ultra thin gate dielectric using a sacrificial polysilicon seed layer A method is presented for forming a transistor wherein polysilicon is preferably deposited upon a dielectric-covered substrate to form a sacrificial polysilicon layer. The sacrificial polysilicon layer may then be reduced to a desired thickness. Thickness... | 03/11/2003 |
| 6504218 | Asymmetrical N-channel and P-channel devices An asymmetrical N-channel IGFET and an asymmetrical P-channel IGFET are disclosed. One or both IGFETs include a lightly doped drain region, heavily doped source and drain regions, and an ultra-heavily doped source region. Preferably, the heavily doped sou... | 01/07/2003 |
| 6483157 | Asymmetrical transistor having a barrier-incorporated gate oxide and a graded implant only in the drain-side junction area A transistor fabrication process is provided which derives a benefit from having an asymmetrical LDD structure. A silicon-based substrate is provided. A gate oxide layer is grown across the substrate. The gate oxide layer may be incorporated with barrier ... | 11/19/2002 |
| 6469316 | Test structure to monitor the effects of polysilicon pre-doping Various embodiments of a test circuit and methods of fabricating and using the same are provided. In one aspect, a test circuit includes a semiconductor substrate and a mask thereon that has an opening to enable impurity doping of selected portions of the... | 10/22/2002 |
| 6451657 | Transistor with an ultra short channel length defined by a laterally diffused nitrogen implant A process is disclosed for fabricating a transistor having a channel length that is smaller than lengths resolvable using common photolithography techniques. A gate oxide layer is formed over a lightly doped semiconductor substrate. A gate conductor layer... | 09/17/2002 |
| 6433400 | Semiconductor fabrication employing barrier atoms incorporated at the edges of a trench isolation structure A method for isolating a first active region from a second active region, both of which are configured within a semiconductor substrate. The method comprises forming a dielectric masking layer above a semiconductor substrate. An opening is then formed thr... | 08/13/2002 |
| 6429052 | Method of making high performance transistor with a reduced width gate electrode and device comprising same The present invention is directed to a method for manufacturing a high performance transistor device with a reduced width or "t-shaped" gate electrode. The method disclosed herein comprises forming a gate insulation layer on a semiconducting substrate, fo... | 08/06/2002 |
| 6420220 | Method of forming electrode for high performance semiconductor devices A method is provided for fabricating a semiconductor device, the method including forming a dielectric layer above a structure, forming a silicidable layer above the dielectric layer and forming a conductive layer above the silicidable layer. The method a... | 07/16/2002 |
| 6420730 | Elevated transistor fabrication technique A second transistor is formed a spaced distance above a first transistor. An interlevel dielectric is first deposited upon the upper surface of the first semiconductor substrate and the first transistor. A second semiconductor substrate, preferably compri... | 07/16/2002 |
| 6417539 | High density memory cell assembly and methods A memory cell assembly includes a substrate, a first electrode, and a second electrode layer. The first electrode is disposed over the substrate and the second electrode layer is disposed over the first electrode. The second electrode layer includes two o... | 07/09/2002 |
| 6410967 | Transistor having enhanced metal silicide and a self-aligned gate electrode A transistor and a method for making a transistor are described. A metal layer is formed upon a semiconductor substrate, and a masking layer is formed upon the metal layer. The masking layer is patterned to form an opening therein, and portions of the met... | 06/25/2002 |
| 6410409 | Implanted barrier layer for retarding upward diffusion of substrate dopant Boron forming a deep P+ layer within a semiconductor substrate upwardly diffuses during subsequent heat treatment operations such as annealing. A method for retarding this upward diffusion of boron includes implanting nitrogen to form a nitrogen barrier l... | 06/25/2002 |
| 6403445 | Enhanced trench isolation structure An improved method of trench isolation formation includes, for one embodiment, applying a polysilicon layer above a planarized trench, and converting the polysilicon to oxide prior to etching the active areas. This converted oxide is denser than the mater... | 06/11/2002 |
| 6388298 | Detached drain MOSFET A detached drain transistor including a semiconductor substrate, a source impurity distribution, a drain impurity distribution, a gate dielectric, and a conductive gate. The source impurity distribution is substantially contained within a source region of... | 05/14/2002 |
| 6383874 | In-situ stack for high volume production of isolation regions A device stack for fabrication of an isolation structure and methods of fabricating the same are provided. In one aspect, a method of processing a substrate is provided that includes exposing the substrate to a plasma ambient containing nitrogen and oxyge... | 05/07/2002 |
| 6383872 | Parallel and series-coupled transistors having gate conductors formed on sidewall surfaces of a sacrificial structure An improved series and/or parallel connection of transistors within a logic gate is presented. The improved connection is brought about by a sacrificial structure on which gate conductors are formed adjacent sidewall surfaces of the sacrificial structure.... | 05/07/2002 |
| 6380554 | Test structure for electrically measuring the degree of misalignment between successive layers of conductors The present invention advantageously provides a test structure and method for using electrical measurements to determine the overlay between successive layers of conductors lithographically patterned upon a semiconductor topography. According to an embodi... | 04/30/2002 |
| 6380055 | Dopant diffusion-retarding barrier region formed within polysilicon gate layer A diffusion-retarding barrier region is incorporated into the gate electrode to reduce the downward diffusion of dopant toward the gate dielectric. The barrier region is a nitrogen-containing diffusion retarding barrier region formed between two separatel... | 04/30/2002 |
| 6373113 | Nitrogenated gate structure for improved transistor performance and method for making same An integrated circuit is provided in which nitrogen is incorporated into the gate dielectric and transistor gate. A method for forming the integrated circuit preferably comprises the providing of a semiconductor substrate that has a p-well and a laterally... | 04/16/2002 |
| 6372588 | Method of making an IGFET using solid phase diffusion to dope the gate, source and drain A method of making an IGFET using solid phase diffusion is disclosed. The method includes providing a device region in a semiconductor substrate, forming a gate insulator on the device region, forming a gate on the gate insulator, forming an insulating la... | 04/16/2002 |
| 6365943 | High density integrated circuit A semiconductor transistor which includes a silicon base layer, a gate dielectric formed on the silicon base layer, first and second silicon source/drain structures, first and second spacer structures, and a silicon gate structure is provided. A method fo... | 04/02/2002 |
| 6362510 | Semiconductor topography having improved active device isolation and reduced dopant migration A method for fabricating an integrated circuit is presented wherein a semiconductor substrate is provided having a dielectric layer formed on its upper surface. A groove is formed in the dielectric layer that extends from the upper surface of the semicond... | 03/26/2002 |
| 6358828 | Ultra high density series-connected transistors formed on separate elevational levels A three-dimensional integrated circuit and fabrication process is provided for producing active and passive devices on various levels of the integrated circuit. The present process is particularly suited to interconnecting a source of one transistor to a ... | 03/19/2002 |
| 6355955 | Transistor and a method for forming the transistor with elevated and/or relatively shallow source/drain regions to achieve enhanced gate electrode formation An integrated circuit fabrication process is provided for forming a transistor having shallow effective source/drain regions and/or laterally shortened source/drain regions. In one embodiment a mesa is formed from the semiconductor substrate. The mesa pre... | 03/12/2002 |
| 6326251 | Method of making salicidation of source and drain regions with metal gate MOSFET A method of forming a transistor includes forming a source/drain implant in the initial processing stages just after the formation of the isolation and active regions on the substrate. A uniform nitride layer is formed over the surface of the substrate on... | 12/04/2001 |
| 6323519 | Ultrathin, nitrogen-containing MOSFET sidewall spacers using low-temperature semiconductor fabrication process A transistor and a method for making a transistor are described. A gate conductor is patterned over a gate dielectric upon a semiconductor substrate. Dopant impurity distributions self-aligned to the gate conductor may be introduced. A conformal oxide hav... | 11/27/2001 |
| 6323561 | Spacer formation for precise salicide formation The formation of a spacer for precise salicide formation is disclosed. In one embodiment, a method includes four steps. In the first step, at least one first spacer is formed, where each spacer is adjacent to an edge of a gate on a substrate and has a tri... | 11/27/2001 |
| 6309936 | Integrated formation of LDD and non-LDD semiconductor devices A method of forming a semiconductor device includes forming a first gate electrode over a substrate and then forming a spacer on at least one sidewall of the first gate electrode. A second gate electrode is formed over the substrate after forming the spac... | 10/30/2001 |
| 6306763 | Enhanced salicidation technique A semiconductor fabrication process in which enhanced salicidation and reliability is achieved by implanting a silicon bearing species and a nitrogen bearing species into the source/drain regions and polysilicon regions of an integrated circuit transistor... | 10/23/2001 |
| 6303962 | Dielectrically-isolated transistor with low-resistance metal source and drain formed using sacrificial source and drain structures A transistor is provided and formed using self-aligned low-resistance source and drain regions within a metal-oxide semiconductor (MOS) process. The gate of the transistor may also be formed from a low-resistance material such as a metal. The transistor c... | 10/16/2001 |
