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| Number | Title | Issue Date |
| 7903379 | Cascode I/O driver with improved ESD operation A cascode I/O driver is described that includes a barrier formed in the shared region between the two transistors. The barrier region allows the I/O driver to be designed to primarily meet I/O requirements. Accordingly, improved operating speeds are achieved. An sys... | 03/08/2011 |
| 7253064 | Cascode I/O driver with improved ESD operation A cascode I/O driver is described that includes a barrier formed in the shared region between the two transistors. The barrier region allows the I/O driver to be designed to primarily meet I/O requirements. Accordingly, improved operating speeds are achieved. An sys... | 08/07/2007 |
| 6924522 | EEPROM transistor for a DRAM A floating gate transistor is formed by simultaneously creating buried contact openings on both EEPROM transistor gates and DRAM access transistor source/drain diffusions. Conventional DRAM process steps are used to form cell storage capacitors in all the buried con... | 08/02/2005 |
| 6809386 | Cascode I/O driver with improved ESD operation A cascode I/O driver is described that includes a barrier formed in the shared region between the two transistors. The barrier region allows the I/O driver to be designed to primarily meet I/O requirements. Accordingly, improved operating speeds are achieved. An sys... | 10/26/2004 |
| 6699734 | Method and apparatus for coupling a semiconductor die to die terminals A method and apparatus for coupling a semiconductor die to terminals of a die package in which the die is housed. The apparatus comprises a die having first and second terminals. A first conductive member is elongated between a first end portion and a sec... | 03/02/2004 |
| 6600215 | Method and apparatus for coupling a semiconductor die to die terminals A method and apparatus for coupling a semiconductor die to terminals of a die package in which the die is housed. The apparatus comprises a die having first and second terminals. A first conductive member is elongated between a first end portion and a sec... | 07/29/2003 |
| 6586290 | Structure for ESD protection in semiconductor chips An ESD protection structure for I/O pads is formed with well resistors underlying the active areas of a transistor. The well resistors are coupled in series with the active areas and provide additional resistance which is effective in protecting the trans... | 07/01/2003 |
| 6579746 | Method and apparatus for coupling a semiconductor die to die terminals A method and apparatus for coupling a semiconductor die to terminals of a die package in which the die is housed. The apparatus comprises a die having first and second terminals. A first conductive member is elongated between a first end portion and a sec... | 06/17/2003 |
| 6507074 | Structure for ESD protection in semiconductor chips An ESD protection structure for I/O pads is formed with well resistors underlying the active areas of a transistor The well resistors are coupled in series with the active areas and provide additional resistance which is effective in protecting the transi... | 01/14/2003 |
| 6504396 | Method for adjusting an output slew rate of a buffer A buffer with an adjustable slew rate, including a current driver having an input terminal and an enable circuit connected to the input terminal to selectively enables the current driver. In one embodiment, the current driver includes an input terminal an... | 01/07/2003 |
| 6391755 | Method of making EEPROM transistor for a DRAM A floating gate transistor is formed by simultaneously creating buried contact openings on both EEPROM transistor gates and DRAM access transistor source/drain diffusions. Conventional DRAM process steps are used to form cell storage capacitors in all the... | 05/21/2002 |
| 6356250 | Matrix addressable display with electrostatic discharge protection A field emission display includes electrostatic discharge protection circuits coupled to an emitter substrate and an extraction grid. In the preferred embodiment, the electrostatic discharge circuit includes diodes reverse biased between grid sections and... | 03/12/2002 |
| 6300788 | Buffer with adjustable slew rate and a method of providing an adjustable slew rate A buffer with an adjustable slew rate, including a current driver having an input terminal and an enable circuit connected to the input terminal to selectively enables the current driver. In one embodiment, the current driver includes an input terminal an... | 10/09/2001 |
| 6300668 | High resistance integrated circuit resistor The present invention teaches fabrication of a high-resistance integrated circuit diffusion resistor that uses standard CMOS process steps. By appropriate masking during ion-implantation of source/drain diffusion regions, diffusion resistors created durin... | 10/09/2001 |
| 6266034 | Matrix addressable display with electrostatic discharge protection A field emission display includes electrostatic discharge protection circuits coupled to an emitter substrate and an extraction grid. In the preferred embodiment, the electrostatic discharge circuit includes diodes reverse biased between grid sections and... | 07/24/2001 |
| 6252293 | Laser antifuse using gate capacitor An integrated circuit laser antifuse is described which has two physical states. In the first physical state the laser antifuse has to conductive plates electrically separated by a layer of dielectric material. In the second physical state the two conduct... | 06/26/2001 |
| 6157204 | Buffer with adjustable slew rate and a method of providing an adjustable slew rate A buffer with an adjustable slew rate, including a current driver having an input terminal and an enable circuit connected to the input terminal to selectively enables the current driver. In one embodiment, the current driver includes an input terminal an... | 12/05/2000 |
| 6137664 | Well resistor for ESD protection of CMOS circuits A circuit for providing electrostatic discharge (ESD) protection is disclosed. The circuit comprises a pair of CMOS field effect pull up and pull down transistors with reduced resistance source and drain, having a well resistor formed external to them bet... | 10/24/2000 |
| 6111806 | Memory device with regulated power supply control A memory device is described which includes a voltage regulator having a low power standby mode. A voltage regulator control circuit is described which places the voltage regulator in a high current mode when the outputs of the memory device are active. T... | 08/29/2000 |
| 6069492 | Voltage compensating CMOS input buffer circuit A voltage compensating CMOS input buffer converts input TTL signals to CMOS logic levels, and compensates for changing supply voltage by using a n-channel transistor to vary the effective size ratio of pairs p-channel to n-channel transistors making up an... | 05/30/2000 |
| 6069832 | Method for multiple staged power up of integrated circuit A complementary metal-oxide semiconductor (CMOS) integrated circuit, such as a dynamic random access memory (DRAM), is powered by supply voltage. The CMOS integrated circuit is divided into n circuit portions including a first circuit portion and a second... | 05/30/2000 |
| 6060896 | Super-voltage circuit with a fast reset A super-voltage circuit with a fast reset capability is formed in an integrated circuit for generating a test mode logic state for testing other circuits in the same integrated circuit. The super-voltage circuit includes a sensing circuit, a reset circuit... | 05/09/2000 |
| 6055193 | Charge pump circuits and devices containing such Circuits to convert an input voltage supply to an output voltage supply having a different magnitude or polarity. The circuits include a capacitor having a first terminal and a second terminal, a first switch coupled to the first terminal of the capacitor... | 04/25/2000 |
| 6040608 | Field-effect transistor for one-time programmable nonvolatile memory element A least one one-time programmable nonvolatile (NV) memory element uses a field-effect transistor (FET) as a selectively programmed element. A short duration applied drain voltage exceeding the FET's drain-to-source breakdown voltage results in a drain sou... | 03/21/2000 |
| 6022787 | Method of making a structure for providing signal isolation and decoupling in an integrated circuit device A signal isolation and decoupling structure fabricated in an integrated circuit device for providing signal isolation and decoupling for signal carrying conductors of the integrated circuit device, wherein one of the conductors is embedded in dielectric m... | 02/08/2000 |
| 6011386 | Frequency adjustable, zero temperature coefficient referencing ring oscillator circuit A frequency adjustable, zero temperature coefficient referencing ring oscillator circuit includes a plurality of inverter stages each having a switching circuit that produces the oscillating output signal for the ring oscillator circuit and a control circ... | 01/04/2000 |
| 5990538 | High resistivity integrated circuit resistor The present invention teaches fabrication of a high-resistance integrated circuit diffusion resistor that uses standard CMOS process steps. By appropriate masking during ion-implantation of source/drain diffusion regions, diffusion resistors created durin... | 11/23/1999 |
| 5982599 | Input/output electrostatic discharge protection for devices with multiple individual power groups An electrostatic discharge protection system for an integrated circuit device, such as a solid state memory device or any other integrated circuit device having a plurality of individual power groups, includes a loop of an electrically conductive material... | 11/09/1999 |
| 5946259 | Voltage generator methods and apparatus A reduced threshold voltage (Vt) magnitude or depletion mode metal-oxide-semiconductor (MOS) capacitor capable of use in a charge pump circuit such as a substrate bias voltage generator in a dynamic random access memory (DRAM) integrated circuit. The Vt m... | 08/31/1999 |
| 5923899 | System for generating configuration output signal responsive to configuration input signal, enabling configuration, and providing status signal identifying enabled configuration responsive to the output signal A configurable integrated circuit has first and second externally accessible terminals. A configuration circuit has an input terminal coupled to the first externally accessible terminal and also has an output terminal. The configuration circuit receives a... | 07/13/1999 |
| 5907518 | Memory device with regulated power supply control A memory device is described which includes a voltage regulator having a low power standby mode. A voltage regulator control circuit is described which places the voltage regulator in a high current mode when the outputs of the memory device are active. T... | 05/25/1999 |
| 5880917 | Well resistor for ESD protection of CMOS circuits A circuit for providing electrostatic discharge (ESD) protection is disclosed. The circuit comprises a pair of CMOS field effect pull up and pull down transistors with reduced resistance source and drain, having a well resistor formed external to them bet... | 03/09/1999 |
| 5844370 | Matrix addressable display with electrostatic discharge protection A field emission display includes electrostatic discharge protection circuits coupled to an emitter substrate and an extraction grid. In the preferred embodiment, the electrostatic discharge circuit includes diodes reverse biased between grid sections and... | 12/01/1998 |
| 5834813 | Field-effect transistor for one-time programmable nonvolatile memory element A least one one-time programmable nonvolatile (NV) memory element uses a field-effect transistor (FET) as a selectively programmed element. A short duration applied drain voltage exceeding the FET's drain-to-source breakdown voltage results in a drain sou... | 11/10/1998 |
| 5811869 | Laser antifuse using gate capacitor An integrated circuit laser antifuse is described which has two physical states. In the first physical state the laser antifuse has to conductive plates electrically separated by a layer of dielectric material. In the second physical state the two conduct... | 09/22/1998 |
| 5801421 | Staggered contact placement on CMOS chip A method and apparatus for increasing the number of contacts provided between two conductive layers separated by an insulator in a semiconductor integrated circuit chip is disclosed. In a first row of contacts, each contact in the row is separated by a di... | 09/01/1998 |
| 5781490 | Multiple staged power up of integrated circuit A complementary metal-oxide semiconductor (CMOS) integrated circuit, such as a dynamic random access memory (DRAM), is powered by supply voltage. The CMOS integrated circuit is divided into n circuit portions including a first circuit portion and a second... | 07/14/1998 |
| 5767552 | Structure for ESD protection in semiconductor chips An ESD protection structure for I/O pads is formed with well resistors underlying the active areas of a transistor. The well resistors are coupled in series with the active areas and provide additional resistance which is effective in protecting the trans... | 06/16/1998 |
| 5744839 | ESD protection using selective siliciding techniques The present invention relates to methods and apparatus for manufacturing semiconductor devices, and in particular for forming electrostatic discharge (ESD) protection devices, using selective siliciding, in a CMOS integrated circuit. Predetermined dischar... | 04/28/1998 |
| 5729047 | Method and structure for providing signal isolation and decoupling in an integrated circuit device A signal isolation and decoupling structure fabricated in an integrated circuit device for providing signal isolation and decoupling for signal carrying conductors of the integrated circuit device, wherein one of the conductors is embedded in dielectric m... | 03/17/1998 |
