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| Number | Title | Issue Date |
| RE38674 | Process for forming a thin oxide layer A novel process for forming a robust, sub-100 Å oxide is disclosed. Native oxide growth is tightly controlled by flowing pure nitrogen during wafer push and nitrogen with a small amount of oxygen during temperature ramp and stabilization. First, a dry oxidation is... | 12/21/2004 |
| 6326664 | Transistor with ultra shallow tip and method of fabrication A novel transistor with a low resistance ultra shallow tip region and its method of fabrication. The novel transistor of the present invention has a source/drain extension or tip comprising an ultra shallow region which extends beneath the gate electrode ... | 12/04/2001 |
| 6165826 | Transistor with low resistance tip and method of fabrication in a CMOS process A novel transistor with a low resistance ultra shallow tip region and its method of fabrication in a complementary metal oxide semiconductor (CMOS) process. According to the preferred method of the present invention, a first gate dielectric and a first ga... | 12/26/2000 |
| 6139404 | Apparatus and a method for conditioning a semiconductor wafer polishing pad A semiconductor wafer polishing pad conditioner which includes a support structure and a roller which is rotatably mounted to the support structure. The roller has a working surface which is formed with a plurality of blades.... | 10/31/2000 |
| 6095904 | Orbital motion chemical-mechanical polishing method and apparatus A method and apparatus for polishing a thin film formed on a semiconductor substrate. A table covered with a polishing pad is orbited about an axis. Slurry is fed through a plurality of spaced-apart holes formed through the polishing pad to uniformly dist... | 08/01/2000 |
| 5863832 | Capping layer in interconnect system and method for bonding the capping layer onto the interconnect system The present invention provides an interconnect system. The interconnect system includes a substrate, a first dielectric layer deposited upon the substrate. The interconnect system further includes at least two electrically conductive interconnect lines fo... | 01/26/1999 |
| 5856697 | Integrated dual layer emitter mask and emitter trench for BiCMOS processes A new method of isolating a polysilicon emitter from the base region of a bipolar transistor, trenching the polysilicon emitter into the semiconductor substrate, and maintaining a consistent base width of a bipolar transistor independent of variations in ... | 01/05/1999 |
| 5783478 | Method of frabricating a MOS transistor having a composite gate electrode A novel, reliable, high performance MOS transistor with a composite gate electrode which is compatible with standard CMOS fabrication processes. The composite gate electrode comprises a polysilicon layer formed on a highly conductive layer. The composite ... | 07/21/1998 |
| 5710450 | Transistor with ultra shallow tip and method of fabrication A novel transistor with a low resistance ultra shallow tip region and its method of fabrication. The novel transistor of the present invention has a source/drain extension or tip region comprising an ultra shallow region which extends beneath the gate ele... | 01/20/1998 |
| 5625217 | MOS transistor having a composite gate electrode and method of fabrication A novel, reliable, high performance MOS transistor with a composite gate electrode which is compatible with standard CMOS fabrication processes. The composite gate electrode comprises a polysilicon layer formed on a highly conductive layer. The composite ... | 04/29/1997 |
| 5611943 | Method and apparatus for conditioning of chemical-mechanical polishing pads A method and apparatus for conditioning and/or rinsing a pad in a chemical-mechanical polisher. A scoring apparatus is rotated about its center directly over the polishing pad of the chemical-mechanical polisher. The scoring apparatus scores the pad surfa... | 03/18/1997 |
| 5595526 | Method and apparatus for endpoint detection in a chemical/mechanical process for polishing a substrate A method for polishing the surface of a substrate that overcomes the problems inherent in the prior art. During the polishing of a substrate, a quantity is calculated which is approximately proportional to a share of the total energy the polisher is consu... | 01/21/1997 |
| 5554064 | Orbital motion chemical-mechanical polishing apparatus and method of fabrication A method and apparatus for polishing a thin film formed on a semiconductor substrate. A table covered with a polishing pad is orbited about an axis. Slurry is fed through a plurality of spaced-apart holes formed through the polishing pad to uniformly dist... | 09/10/1996 |
| 5488003 | Method of making emitter trench BiCMOS using integrated dual layer emitter mask A new method of isolating a polysilicon emitter from the base region of a bipolar transistor, trenching the polysilicon emitter into the semiconductor substrate, and maintaining a consistent base width of a bipolar transistor independent of variations in ... | 01/30/1996 |
| 5434093 | Inverted spacer transistor A method for forming narrow length transistors by forming a trench in a first layer over a semiconductor substrate. Spacers are then formed within the trench and a gate dielectric is formed between the spacers at the bottom of the trench on the semiconduc... | 07/18/1995 |
| 5244843 | Process for forming a thin oxide layer A novel process for forming a robust, sub-100 Å oxide is disclosed. Native oxide growth is tightly controlled by flowing pure nitrogen during wafer push and nitrogen with a small amount of oxygen during temperature ramp and stabilization. First, a dry ox... | 09/14/1993 |
| 5104819 | Fabrication of interpoly dielctric for EPROM-related technologies A method and a device formed by the method of forming a composite dielectric structure between the floating polysilicon electrode and the control electrode of an EPROM-type device is disclosed. The dielectic is characterized by a thin (0-80 angstroms) the... | 04/14/1992 |
| 4917044 | Electrical contact apparatus for use with plasma or glow discharge reaction chamber An electrical contact apparatus for use in a plama or glow discharge chamber, particularly a chamber for depositing silicon oxynitride. A feedthrough member provides an electrical path between the interior and exterior of the chamber. An electrical contac... | 04/17/1990 |
| 4837185 | Pulsed dual radio frequency CVD process A method of depositing a thin film of silicon oxynitride (Six Oy Nz) onto a semiconductor substrate utilizing dual frequency plasma enhanced chemical vapor deposition (PECVD). Plasma formation is achieved by striking gases... | 06/06/1989 |
| 4786612 | Plasma enhanced chemical vapor deposited vertical silicon nitride resistor An improved resistor for use in MOS integrated circuits. An opening is formed in an insulative layer which separates two conductive regions. A plasma enhanced chemical vapor deposition of passivation material such as silicon-rich silicon nitride is deposi... | 11/22/1988 |
| 4755480 | Method of making a silicon nitride resistor using plasma enhanced chemical vapor deposition An improved resistor for use in MOS integrated circuits. An opening is formed in an insulative layer which separates two conductive regions. A plasma enhanced chemical vapor deposition of passivation material such as silicon-rich silcon nitride is deposit... | 07/05/1988 |
| 4690728 | Pattern delineation of vertical load resistor A process for delineating a vertical resistor on a semiconductor device is disclosed. Resistive and diffusion barrier layers are deposited and then etched, first by dry plasma and then by wet bath. The two step etching allows complete removal of the depos... | 09/01/1987 |