Bizarre Patents
A small umbrella which may be removably attached to a beverage container in order to shade the beverage container from the direct rays of the sun.
PatentStorm News
Make the Most of PatentStorm
See this month's Top Inventors and Most Cited Patents.
Stay on top of the latest patents by subscribing to an RSS feed.
Got questions? Ask a Patent Expert!
Registered users: Manage your profile, comments and alerts.
| Number | Title | Issue Date |
| 7221605 | Switched capacitor DRAM sense amplifier with immunity to mismatch and offsets A switched capacitor sense amplifier includes capacitively coupled input, feedback, and reset paths to provide immunity to the mismatches in transistor characteristics and offsets. The sense amplifier includes a cross-coupled pair of inverters with capacitors absorb... | 05/22/2007 |
| 7217606 | Method of forming vertical sub-micron CMOS transistors on (110), (111), (311), (511), and higher order surfaces of bulk, soi and thin film structures A method for forming NMOS and PMOS transistors that includes cutting a substrate along a higher order orientation and fabricating deep sub-micron NMOS and PMOS transistors on the vertical surfaces thereof. The complementary NMOS and PMOS transistors form a CMOS tran... | 05/15/2007 |
| 7217974 | Output prediction logic circuits with ultra-thin vertical transistors and methods of formation Very fast integrated OPL circuits, such as pseudo-NMOS OPL and dynamic OPL, comprising CMOS gate arrays having ultra-thin vertical NMOS transistors are disclosed. The ultra-thin vertical NMOS transistors of the CMOS gate arrays are formed with relaxed silicon german... | 05/15/2007 |
| 7214616 | Homojunction semiconductor devices with low barrier tunnel oxide contacts A homojunction bipolar transistor with performance characteristics similar to more costly heterojunction or retrograde base transistors. The high emitter resistivity found in prior homojunction devices is circumvented using a low work function material layer in form... | 05/08/2007 |
| 7214994 | Self aligned metal gates on high-k dielectrics A method for forming a transistor including a self aligned metal gate is provided. According to various method embodiments, a high-k gate dielectric is formed on a substrate and a sacrificial carbon gate is formed on the gate dielectric. Sacrificial carbon sidewall ... | 05/08/2007 |
| 7211512 | Selective electroless-plated copper metallization Structures and methods are provided which include a selective electroless copper metallization. The present invention includes a novel methodology for forming copper vias on a substrate. This method includes depositing a thin film seed layer of Palladium (Pd) or Cop... | 05/01/2007 |
| 7211492 | Self aligned metal gates on high-k dielectrics A method for forming a transistor including a self aligned metal gate is provided. According to various method embodiments, a high-k gate dielectric is formed on a substrate and a sacrificial carbon gate is formed on the gate dielectric. Sacrificial carbon sidewall ... | 05/01/2007 |
| 7208804 | Crystalline or amorphous medium-K gate oxides, Y0and Gd0 A gate oxide and method of fabricating a gate oxide that produces a more reliable and thinner equivalent oxide thickness than conventional SiO2 gate oxides are provided. Also shown is a gate oxide with a conduction band offset of 2 eV or greater. Gate oxi... | 04/24/2007 |
| 7205620 | Highly reliable amorphous high-k gate dielectric ZrON A gate dielectric and method of fabricating a gate dielectric that produces a more reliable and thinner equivalent oxide thickness than conventional SiO2 gate oxides are provided. Gate dielectrics formed from metals such as zirconium are thermodynamically... | 04/17/2007 |
| 7205218 | Method including forming gate dielectrics having multiple lanthanide oxide layers A dielectric film having a layer of a lanthanide oxide and a layer of another lanthanide oxide, and a method of fabricating such a dielectric film produce a reliable gate dielectric with a equivalent oxide thickness thinner than attainable using SiO2. A g... | 04/17/2007 |
| 7202739 | CMOS amplifiers with frequency compensating capacitors The frequency and transient responses of a CMOS differential amplifier are improved by employing one or more compensating capacitors. A compensating capacitor coupled to a differential input of the CMOS differential amplifier is used to inject current into the diffe... | 04/10/2007 |
| 7202523 | NROM flash memory devices on ultrathin silicon An NROM flash memory cell is implemented in an ultra-thin silicon-on-insulator structure. In a planar device, the channel between the source/drain areas is normally fully depleted. An oxide layer provides an insulation layer between the source/drain areas and the ga... | 04/10/2007 |
| 7202530 | Micro-mechanically strained semiconductor film One aspect of the present subject matter relates to a method for forming strained semiconductor film. In various embodiments, a single crystalline semiconductor film is formed on a substrate surface, and a recess is created beneath the film. A portion of the film is... | 04/10/2007 |
| 7199023 | Atomic layer deposited HfSiON dielectric films wherein each precursor is independendently pulsed A dielectric film containing atomic layer deposited HfSiON and a method of fabricating such a dielectric film produce a reliable dielectric layer having an equivalent oxide thickness thinner than attainable using SiO2. The HfSiON layer thickness is contro... | 04/03/2007 |
| 7199417 | Merged MOS-bipolar capacitor memory cell A high density vertical merged MOS-bipolar-capacitor gain cell is realized for DRAM operation. The gain cell includes a vertical MOS transistor having a source region, a drain region, and a floating body region therebetween. The gain cell includes a vertical bi-pola... | 04/03/2007 |
| 7198999 | Flash memory device having a graded composition, high dielectric constant gate insulator A graded composition, high dielectric constant gate insulator is deposited between a substrate and floating gate in a flash memory cell transistor. If the composition of the gate insulator is closer to the high-k material near the substrate, the electron barrier for... | 04/03/2007 |
| 7198974 | Micro-mechanically strained semiconductor film One aspect of the present subject matter relates to a method for forming strained semiconductor film. In various embodiments, a single crystalline semiconductor film is formed on a substrate surface, and a recess is created beneath the film. A portion of the film is... | 04/03/2007 |
| 7200046 | Low power NROM memory devices A buried bipolar junction is provided in a charge trapping transistor memory device. During a write operation electrons are injected into a surface depletion region of the memory cell transistors. These electrons are accelerated in a vertical electric field and inje... | 04/03/2007 |
| 7195999 | Metal-substituted transistor gates One aspect of this disclosure relates to a method for forming a transistor. According to various method embodiments, a gate dielectric is formed on a substrate, a substitutable structure is formed on the gate dielectric, and source/drain regions for the transistor a... | 03/27/2007 |
| 7196929 | Method for operating a memory device having an amorphous silicon carbide gate insulator A floating gate transistor has a reduced barrier energy at an interface with an adjacent amorphous silicon carbide (a-SiC) gate insulator, allowing faster charge transfer across the gate insulator at lower voltages. Data is stored as charge on the floating gate. The... | 03/27/2007 |
| 7196935 | Ballistic injection NROM flash memory A split NROM flash memory cell is comprised of source/drain regions in a substrate. The split nitride charge storage regions are insulated from the substrate by a first layer of oxide material and from a control gate by a second layer of oxide material. The nitride ... | 03/27/2007 |
| 7196936 | Ballistic injection NROM flash memory A split NROM flash memory cell is comprised of source/drain regions in a substrate. The split nitride charge storage regions are insulated from the substrate by a first layer of oxide material and from a control gate by a second layer of oxide material. The nitride ... | 03/27/2007 |
| 7193893 | Write once read only memory employing floating gates Structures and methods for write once read only memory employing floating gates are provided. The write once read only memory cell includes a floating gate transistor formed in a modified dynamic random access memory (DRAM) fabrication process. The floating gate tra... | 03/20/2007 |
| 7192892 | Atomic layer deposited dielectric layers An atomic layer deposited dielectric layer and a method of fabricating such a dielectric layer produce a reliable dielectric layer having an equivalent oxide thickness thinner than attainable using SiO2. Depositing a hafnium metal layer on a substrate sur... | 03/20/2007 |
| 7192827 | Methods of forming capacitor structures The invention includes a method of forming a capacitor structure. A first electrical node is formed, and a layer of metallic aluminum is formed over the first electrical node. Subsequently, an entirety of the metallic aluminum within the layer is transformed into on... | 03/20/2007 |
| 7192824 | Lanthanide oxide / hafnium oxide dielectric layers Dielectric layers containing an atomic layer deposited hafnium oxide and an electron beam evaporated lanthanide oxide and a method of fabricating such a dielectric layer produce a reliable dielectric layer having an equivalent oxide thickness thinner than attainable... | 03/20/2007 |
| 7190020 | Non-planar flash memory having shielding between floating gates A first plurality of memory cells is formed on pillars in a first column of the array. A second plurality of memory cells is formed in a first set of trenches in the same column. The second plurality of memory cells is coupled to the first plurality of memory cells ... | 03/13/2007 |
| 7190616 | In-service reconfigurable DRAM and flash memory device A memory cell that has both a DRAM cell and a non-volatile memory cell. The non-volatile memory cell might include a flash memory or an NROM cell. The memory cell is comprised of a vertical floating body transistor with dual gates, one on either side of a vertical p... | 03/13/2007 |
| 7190736 | Technique to simultaneously distribute clock signals and data on integrated circuits, interposers, and circuit boards A technique is described for simultaneously and synchronously transmitting digital data and a clock signal in a digital integrated circuit, circuit board, or system. The technique is based on the phase shift keying (PSK) modulation of an RF high frequency carrier wh... | 03/13/2007 |
| 7186664 | Methods and structures for metal interconnections in integrated circuits A typical integrated-circuit fabrication requires interconnecting millions of microscopic transistors and resistors with metal wires. Making the metal wires flush, or coplanar, with underlying insulation requires digging trenches in the insulation, and then filling ... | 03/06/2007 |
| 7187587 | Programmable memory address and decode circuits with low tunnel barrier interpoly insulators Structures and methods for programmable memory address and decode circuits with low tunnel barrier interpoly insulators are provided. The decoder for a memory device includes a number of address lines and a number of output lines wherein the address lines and the ou... | 03/06/2007 |
| 7184315 | NROM flash memory with self-aligned structural charge separation A nitride read only memory (NROM) cell has a nitride layer that is not located under the center of the transistor. The gate insulator layer, with the nitride layer, is comprised of two sections that each have structurally defined and separated charge trapping region... | 02/27/2007 |
| 7183186 | Atomic layer deposited ZrTiOfilms After pulsing the second purging gas, a zirconium-containing precursor is pulsed into reaction chamber 220, at block 430. In an embodiment, the zirconium-containing precursor is ZTB. In other embodiments, a zirconium-containing precursor includes but i... | 02/27/2007 |
| 7180370 | CMOS amplifiers with frequency compensating capacitors The frequency and transient responses of a CMOS differential amplifier are improved by employing one or more compensating capacitors. A compensating capacitor coupled to a differential input of the CMOS differential amplifier is used to inject current into the diffe... | 02/20/2007 |
| 7177193 | Programmable fuse and antifuse and method therefor P-channel MOSFET devices are used as reprogrammable fuse or antifuse elements in a memory decode circuit by utilizing anomalous hole generation. An applied negative gate bias voltage is sufficiently large to cause tunnel electrons to gain enough energy to exceed the... | 02/13/2007 |
| 7176719 | Capacitively-coupled level restore circuits for low voltage swing logic circuits A level restore circuit includes differential sides and a capacitive network having capacitors cross-coupled between the differential sides to provide a capacitively-coupled positive feedback between the differential sides. The level restore circuit further includes... | 02/13/2007 |
| 7168163 | Full wafer silicon probe card for burn-in and testing and test system including same A full-wafer probe card is disclosed along with related methods and systems. The probe card includes test probes comprising cantilever elements configured and arranged with probe tips in a pattern corresponding to an array of bond pads of semiconductor dice residing... | 01/30/2007 |
| 7169666 | Method of forming a device having a gate with a selected electron affinity A floating gate transistor has a reduced barrier energy at an interface with an adjacent gate insulator, allowing faster charge transfer across the gate insulator at lower voltages. Data is stored as charge on the floating gate. The data charge retention time on the... | 01/30/2007 |
| 7169673 | Atomic layer deposited nanolaminates of HfO/ZrOfilms as gate dielectrics A dielectric film containing HfO2/ZrO2 nanolaminates and a method of fabricating such a dielectric film produce a reliable gate dielectric having an equivalent oxide thickness thinner than attainable using SiO2. A gate dielectric is ... | 01/30/2007 |
| 7166509 | Write once read only memory with large work function floating gates Structures and methods for write once read only memory employing floating gates are provided. The write once read only memory cell includes a floating gate transistor formed in a modified dynamic random access memory (DRAM) fabrication process. The floating gate tra... | 01/23/2007 |