Famous Patents
The first commercial microwave oven was nearly 6 feet tall and weighed in at 750 pounds.
PatentStorm News
Make the Most of PatentStorm
See this month's Top Inventors and Most Cited Patents.
Stay on top of the latest patents by subscribing to an RSS feed.
Got questions? Ask a Patent Expert!
Registered users: Manage your profile, comments and alerts.
| Number | Title | Issue Date |
| 7045430 | Atomic layer-deposited LaAlO3 films for gate dielectrics A dielectric film containing LaAlO3 and method of fabricating a dielectric film contained LaAlO3 produce a reliable gate dielectric having a thinner equivalent oxide thickness than attainable using SiO2. The LaAlO3 gate di... | 05/16/2006 |
| 7042043 | Programmable array logic or memory devices with asymmetrical tunnel barriers Structures and methods for programmable array type logic and/or memory devices with asymmetrical low tunnel barrier intergate insulators are provided. The programmable array type logic and/or memory devices include non-volatile memory which has a first source/drain ... | 05/09/2006 |
| 7041575 | Localized strained semiconductor on insulator One aspect of this disclosure relates to a method for straining a transistor body region. In various embodiments, oxygen ions are implanted to a predetermined depth in a localized region of a semiconductor substrate, and the substrate is annealed. Oxide growth withi... | 05/09/2006 |
| 7041341 | Process for the fabrication of oxide films The present invention is related to methods and apparatus for processing weak ferroelectric films on semiconductor substrates, including relatively large substrates, e.g., with 300 millimeter diameter. A ferroelectric film of zinc oxide (ZnO) doped with lithium (Li)... | 05/09/2006 |
| 7042148 | Field emission display having reduced power requirements and method A field emission display includes a substrate and a plurality of emitters formed on columns on the substrate. The display also includes a porous dielectric layer formed on the substrate and the columns. The porous dielectric layer has an opening formed about each of... | 05/09/2006 |
| 7037862 | Dielectric layer forming method and devices formed therewith Embodiments in accordance with the present invention provide alternative materials, and methods of forming such materials, that are effective as dielectric layers. Such embodiments include forming metal-containing dielectric layers over a silicon-containing substrat... | 05/02/2006 |
| 7030725 | Semiconductor device with electrically coupled spiral inductors Multiple coupled inductors are formed in a well in a semiconductor device. The inductors, which preferably are spiral inductors, are strongly coupled with high quality factors. The coupled inductors may be used as efficient signal splitting and combining circuits. | 04/18/2006 |
| 7030436 | Embedded DRAM gain memory cell having MOS transistor body provided with a bi-polar transistor charge injecting means A high density horizontal merged MOS-bipolar gain memory cell is realized for DRAM operation. The gain cell includes a horizontal MOS transistor having a source region, a drain region, and a floating body region therebetween. The gain cell includes a horizontal bi-p... | 04/18/2006 |
| 7027328 | Integrated circuit memory device and method Structures and methods for DEAPROM memory with low tunnel barrier intergate insulators are provided. The DEAPROM memory includes a first source/drain region and a second source/drain region separated by a channel region in a substrate. A floating gate opposes the ch... | 04/11/2006 |
| 7026694 | Lanthanide doped TiOdielectric films by plasma oxidation A dielectric film containing lanthanide doped TiOx and a method of fabricating such a dielectric film produce a reliable gate dielectric having an equivalent oxide thickness thinner than attainable using SiO2. A dielectric film is formed by ion... | 04/11/2006 |
| 7023316 | Semiconductor device with electrically coupled spiral inductors Multiple coupled inductors are formed in a well in a semiconductor device. The inductors, which preferably are spiral inductors, are strongly coupled with high quality factors. The coupled inductors may be used as efficient signal splitting and combining circuits. | 04/04/2006 |
| 7023051 | Localized strained semiconductor on insulator One aspect of this disclosure relates to a method for straining a transistor body region. In various embodiments, oxygen ions are implanted to a predetermined depth in a localized region of a semiconductor substrate, and the substrate is annealed. Oxide growth withi... | 04/04/2006 |
| 7023040 | DRAM technology compatible processor/memory chips The present invention includes a programmable logic array having a first logic plane that receives a number of input signals. The first logic plane has a plurality of non-volatile memory cells arranged in rows and columns that are interconnected to provide a number ... | 04/04/2006 |
| 7022553 | Compact system module with built-in thermoelectric cooling An improved integrated circuit package for providing built-in heating or cooling to a semiconductor chip is provided. The improved integrated circuit package provides increased operational bandwidth between different circuit devices, e.g. logic and memory chips. The... | 04/04/2006 |
| 7020030 | SRAM cell with horizontal merged devices A merged structure SRAM cell is provided that includes a first transistor and a second transistor. The second transistor gate forms a load resistor for the first transistor and the first transistor gate forms a load resistor for the second transistor. Also provided ... | 03/28/2006 |
| 7018467 | Three-dimensional complete bandgap photonic crystal formed by crystal modification A method of forming a three-dimensional (3D) complete photonic bandgap crystal by crystal modification is disclosed. The 3D crystal includes a first periodic array of unit cells formed from first voids connected by imaginary bonds. The first periodic array forms an ... | 03/28/2006 |
| 7015525 | Folded bit line DRAM with vertical ultra thin body transistors A folded bit line DRAM device is provided. The folded bit line DRAM device includes an array of memory cells. Each memory cell in the array of memory cells includes a pillar extending outwardly from a semiconductor substrate. Each pillar includes a single crystallin... | 03/21/2006 |
| 7008854 | Silicon oxycarbide substrates for bonded silicon on insulator A method for forming a semiconductor on insulator structure includes forming a semiconductor layer on an insulating substrate, where the substrate is a different material than the semiconductor layer, and has a coefficient of thermal expansion substantially equal to... | 03/07/2006 |
| 7005344 | Method of forming a device with a gallium nitride or gallium aluminum nitride gate A floating gate transistor has a reduced barrier energy at an interface between a gallium nitride (GaN) or gallium aluminum nitride (GaAlN) floating gate an adjacent gate insulator, allowing faster charge transfer across the gate insulator at lower voltages. Data is... | 02/28/2006 |
| 6999351 | Computer systems, processes for turning a SRAM cell off, and processes for writing a SRAM cell and processes for reading data from a SRAM cell A two-transistor SRAM cell includes a first FET. The first FET is an ultrathin FET of a first polarity type and includes a control electrode, a first load electrode and a second electrode. The first load electrode is coupled to a first control line. The SRAM cell al... | 02/14/2006 |
| 6998311 | Methods of forming output prediction logic circuits with ultra-thin vertical transistors Very fast integrated OPL circuits, such as pseudo-NMOS OPL and dynamic OPL, comprising CMOS gate arrays having ultra-thin vertical NMOS transistors are disclosed. The ultra-thin vertical NMOS transistors of the CMOS gate arrays are formed with relaxed silicon german... | 02/14/2006 |
| 6996009 | NOR flash memory cell with high storage density Structures and methods for NOR flash memory cells, arrays and systems are provided. The NOR flash memory cell includes a vertical floating gate transistor extending outwardly from a substrate. The floating gate transistor having a first source/drain region, a second... | 02/07/2006 |
| 6995470 | Multilevel copper interconnects with low-k dielectrics and air gaps Structures and methods are provided for an improved multilevel wiring interconnect in an integrated circuit assembly. The present invention provides for a multilayer copper wiring structure by electroless, selectively deposited copper in a streamlined process which ... | 02/07/2006 |
| 6995443 | Integrated circuits using optical fiber interconnects formed through a semiconductor wafer An integrated circuit with a number of optical fibers that are formed in high aspect ratio holes. The high aspect ratio holes extend through a semiconductor wafer. The optical fibers include a cladding layer and a core formed in the high aspect ratio hole. These opt... | 02/07/2006 |
| 6995441 | Integrated circuits using optical waveguide interconnects formed through a semiconductor wafer and methods for forming same An integrated circuit with a number of optical waveguides that are formed in high aspect ratio holes. The high aspect ratio holes extend through a semiconductor wafer. The optical waveguides include a highly reflective material that is deposited so as to line an inn... | 02/07/2006 |
| 6995057 | Folded bit line DRAM with vertical ultra thin body transistors A folded bit line DRAM device is provided. The folded bit line DRAM device includes an array of memory cells. Each memory cell in the array of memory cells includes a pillar extending outwardly from a semiconductor substrate. Each pillar includes a single crystallin... | 02/07/2006 |
| 6992871 | Microtransformer for system-on-chip power supply A microtransformer for a high-performance system-on-chip power supply is disclosed. Through-wafer openings in a substrate allow the primary and secondary wiring on both surfaces of the silicon substrate. An insulating silicon oxide layer is first deposited on all su... | 01/31/2006 |
| 6991988 | Static pass transistor logic with transistors with multiple vertical gates Static pass transistor logic having transistors with multiple vertical gates are described. Multiple vertical gates are edge defined with only a single transistor being required for multiple logic inputs. Thus a minimal surface area is required for each logic input.... | 01/31/2006 |
| 6990023 | Horizontal memory devices with vertical gates Structures and methods for memory devices are provided which operate with lower control gate voltages than conventional floating gate transistors, and which do not increase the costs or complexity of the device fabrication process. The novel memory cell includes a s... | 01/24/2006 |
| 6989573 | Lanthanide oxide/zirconium oxide atomic layer deposited nanolaminate gate dielectrics The invention provides a laminated dielectric layer for semiconductor devices formed by a combination of ZrO2 and a lanthanide oxide on a semiconductor substrate and methods of making the same. In certain methods, the ZrO2 is deposited by multi... | 01/24/2006 |
| 6989335 | Composite dielectric forming methods and composite dielectrics A composite dielectric forming method includes atomic layer depositing alternate layers of hafnium oxide and lanthanum oxide over a substrate. The hafnium oxide can be thermally stable, crystalline hafnium oxide and the lanthanum oxide can be thermally stable, cryst... | 01/24/2006 |
| 6987037 | Strained Si/SiGe structures by ion implantation One aspect of this disclosure relates to a method for forming a strained silicon over silicon germanium (Si/SiGe) structure. In various embodiments, germanium ions are implanted into a silicon substrate with a desired dose and energy to be located beneath a surface ... | 01/17/2006 |
| 6984891 | Methods for making copper and other metal interconnections in integrated circuits A typical integrated-circuit fabrication requires interconnecting millions of microscopic transistors and resistors with aluminum wires. Yet, aluminum wires have greater electrical resistance and are less reliable than copper wires. Unfortunately, current techniques... | 01/10/2006 |
| 6984886 | System-on-a-chip with multi-layered metallized through-hole interconnection The present invention is directed to a high-performance system on a chip which uses multi-layer wiring/insulation through-hole interconnections to provide short wiring and controlled low-impedance wiring including ground planes and power supply distribution planes b... | 01/10/2006 |
| 6980033 | Pseudo CMOS dynamic logic with delayed clocks Structures and methods for pseudo-CMOS dynamic logic with delayed clocks are provided. A pseudo-CMOS dynamic logic circuit with delayed clocks includes a dynamic pseudo-nMOS logic gate and a dynamic pseudo-pMOS logic gate coupled thereto. The dynamic pseudo-nMOS log... | 12/27/2005 |
| 6979857 | Apparatus and method for split gate NROM memory A split gate, vertical NROM memory cell is comprised of a plurality of oxide pillars that each has a source/drain region formed in the top of the pillar. A trench is formed between each pair of oxide pillars. A polysilicon control gate is formed in the trench betwee... | 12/27/2005 |
| 6979607 | Technique to control tunneling currents in DRAM capacitors, cells, and devices Structures and methods are provided for the use with PMOS devices. Materials with large electron affinities or work functions are provided for structures such as gates. A memory cell is provided that utilizes materials with work functions larger than n-type doped po... | 12/27/2005 |
| 6979855 | High-quality praseodymium gate dielectrics A praseodymium (Pr) gate oxide and method of fabricating same that produces a high-quality and ultra-thin equivalent oxide thickness as compared to conventional SiO2 gate oxides are provided. The Pr gate oxide is thermodynamically stable so that the oxide... | 12/27/2005 |
| 6976300 | Integrated circuit inductors The invention relates to an inductor comprising a plurality of interconnected conductive segments interwoven with a substrate. The inductance of the inductor is increased through the use of coatings and films of ferromagnetic materials such as magnetic metals, alloy... | 12/20/2005 |
| 6975531 | 6F2 3-transistor DRAM gain cell A high density vertical three transistor memory cell is provided. The high density vertical three transistor memory cell is formed in a vertical pillar. The vertical pillar includes a first vertical transfer device having a source region, a drain region, and a body ... | 12/13/2005 |