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A method of swing on a swing is disclosed, in which a user positioned on a standard swing suspended by two chains from a substantially horizontal tree branch induces side to side motion by pulling alternately on one chain and then the other.
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| Number | Title | Issue Date |
| 7186664 | Methods and structures for metal interconnections in integrated circuits A typical integrated-circuit fabrication requires interconnecting millions of microscopic transistors and resistors with metal wires. Making the metal wires flush, or coplanar, with underlying insulation requires digging trenches in the insulation, and then filling ... | 03/06/2007 |
| 7187587 | Programmable memory address and decode circuits with low tunnel barrier interpoly insulators Structures and methods for programmable memory address and decode circuits with low tunnel barrier interpoly insulators are provided. The decoder for a memory device includes a number of address lines and a number of output lines wherein the address lines and the ou... | 03/06/2007 |
| 7183186 | Atomic layer deposited ZrTiOfilms After pulsing the second purging gas, a zirconium-containing precursor is pulsed into reaction chamber 220, at block 430. In an embodiment, the zirconium-containing precursor is ZTB. In other embodiments, a zirconium-containing precursor includes but i... | 02/27/2007 |
| 7184315 | NROM flash memory with self-aligned structural charge separation A nitride read only memory (NROM) cell has a nitride layer that is not located under the center of the transistor. The gate insulator layer, with the nitride layer, is comprised of two sections that each have structurally defined and separated charge trapping region... | 02/27/2007 |
| 7180370 | CMOS amplifiers with frequency compensating capacitors The frequency and transient responses of a CMOS differential amplifier are improved by employing one or more compensating capacitors. A compensating capacitor coupled to a differential input of the CMOS differential amplifier is used to inject current into the diffe... | 02/20/2007 |
| 7177193 | Programmable fuse and antifuse and method therefor P-channel MOSFET devices are used as reprogrammable fuse or antifuse elements in a memory decode circuit by utilizing anomalous hole generation. An applied negative gate bias voltage is sufficiently large to cause tunnel electrons to gain enough energy to exceed the... | 02/13/2007 |
| 7176719 | Capacitively-coupled level restore circuits for low voltage swing logic circuits A level restore circuit includes differential sides and a capacitive network having capacitors cross-coupled between the differential sides to provide a capacitively-coupled positive feedback between the differential sides. The level restore circuit further includes... | 02/13/2007 |
| 7168163 | Full wafer silicon probe card for burn-in and testing and test system including same A full-wafer probe card is disclosed along with related methods and systems. The probe card includes test probes comprising cantilever elements configured and arranged with probe tips in a pattern corresponding to an array of bond pads of semiconductor dice residing... | 01/30/2007 |
| 7169666 | Method of forming a device having a gate with a selected electron affinity A floating gate transistor has a reduced barrier energy at an interface with an adjacent gate insulator, allowing faster charge transfer across the gate insulator at lower voltages. Data is stored as charge on the floating gate. The data charge retention time on the... | 01/30/2007 |
| 7169673 | Atomic layer deposited nanolaminates of HfO/ZrOfilms as gate dielectrics A dielectric film containing HfO2/ZrO2 nanolaminates and a method of fabricating such a dielectric film produce a reliable gate dielectric having an equivalent oxide thickness thinner than attainable using SiO2. A gate dielectric is ... | 01/30/2007 |
| 7166509 | Write once read only memory with large work function floating gates Structures and methods for write once read only memory employing floating gates are provided. The write once read only memory cell includes a floating gate transistor formed in a modified dynamic random access memory (DRAM) fabrication process. The floating gate tra... | 01/23/2007 |
| 7166883 | Capacitor structures The invention includes a method of forming a capacitor structure. A first electrical node is formed, and a layer of metallic aluminum is formed over the first electrical node. Subsequently, an entirety of the metallic aluminum within the layer is transformed into on... | 01/23/2007 |
| 7166886 | DRAM cells with repressed floating gate memory, low tunnel barrier interpoly insulators Structures and methods for memory cells having a volatile and a non-volatile component in a single memory cell are provided. The memory cell includes a first source/drain region and a second source/drain region separated by a channel region in a substrate. A storage... | 01/23/2007 |
| 7164597 | Computer systems A two-transistor SRAM cell includes a first FET. The first FET is an ultrathin FET of a first polarity type and includes a control electrode, a first load electrode and a second electrode. The first load electrode is coupled to a first control line. The SRAM cell al... | 01/16/2007 |
| 7164156 | Electronic systems using optical waveguide interconnects formed throught a semiconductor wafer An integrated circuit with a number of optical waveguides that are formed in high aspect ratio holes. The high aspect ratio holes extend through a semiconductor wafer. The optical waveguides include a highly reflective material that is deposited so as to line an inn... | 01/16/2007 |
| 7164294 | Method for forming programmable logic arrays using vertical gate transistors One aspect disclosed herein relates to a method for forming a programmable logic array. Various embodiments of the method include forming a first logic plane and a second logic plane, each including a plurality of logic cells interconnected to implement a logical fu... | 01/16/2007 |
| 7164168 | Non-planar flash memory having shielding between floating gates A first plurality of memory cells is formed on pillars in a first column of the array. A second plurality of memory cells is formed in a first set of trenches in the same column. The second plurality of memory cells is coupled to the first plurality of memory cells ... | 01/16/2007 |
| 7161174 | Field-effect transistors having doped aluminum oxide dielectrics Doped aluminum oxide layers having a porous aluminum oxide layer and methods of their fabrication. The porous aluminum oxide layer may be formed by evaporation physical vapor deposition techniques to facilitate formation of a high-purity aluminum oxide layer. A dopa... | 01/09/2007 |
| 7160577 | Methods for atomic-layer deposition of aluminum oxides in integrated circuits The present inventors devised unique atomic-layer deposition systems, methods, and apparatus suitable for aluminum-oxide deposition. One exemplary method entails providing an outer chamber enclosing a substrate, forming an inner chamber within the outer chamber, and... | 01/09/2007 |
| 7157733 | Floating-gate field-effect transistors having doped aluminum oxide dielectrics Doped aluminum oxide layers having a porous aluminum oxide layer and methods of their fabrication. The porous aluminum oxide layer may be formed by evaporation physical vapor deposition techniques to facilitate formation of a high-purity aluminum oxide layer. A dopa... | 01/02/2007 |
| 7157769 | Flash memory having a high-permittivity tunnel dielectric A high permittivity tunneling dielectric is used in a flash memory cell to provide greater tunneling current into the floating gate with smaller gate voltages. The flash memory cell has a substrate with source/drain regions. The high-k tunneling dielectric is formed... | 01/02/2007 |
| 7157771 | Vertical device 4FEEPROM memory EEPROM memory devices and arrays are described that facilitate the use of vertical floating gate memory cells and select gates in NOR or NAND high density memory architectures. Memory embodiments of the present invention utilize vertical select gates and floating ga... | 01/02/2007 |
| 7158004 | Integrated circuit inductors The invention relates to an inductor comprising a plurality of interconnected conductive segments interwoven with a substrate. The inductance of the inductor is increased through the use of coatings and films of ferromagnetic materials such as magnetic metals, alloy... | 01/02/2007 |
| 7158410 | Integrated DRAM-NVRAM multi-level memory An integrated DRAM-NVRAM, multi-level memory cell is comprised of a vertical DRAM device with a shared vertical gate floating plate device. The floating plate device provides enhanced charge storage for the DRAM part of the cell through the shared floating body in a... | 01/02/2007 |
| 7154778 | Nanocrystal write once read only memory for archival storage Structures and methods for write once read only memory employing charge trapping are provided. The write once read only memory cell includes a metal oxide semiconductor field effect transistor (MOSFET) in a substrate. The MOSFET has a first source/drain region, a se... | 12/26/2006 |
| 7154354 | High permeability layered magnetic films to reduce noise in high speed interconnection A structure for magnetically shielded transmission lines for use with high speed integrated circuits having an improved signal to noise ratio, and a method for forming the same are disclosed. At least one magnetic shield structure contains electrically induced magne... | 12/26/2006 |
| 7153753 | Strained Si/SiGe/SOI islands and processes of making same A process of making a strained silicon-on-insulator structure is disclosed. A recess is formed in a substrate to laterally isolate an active area. An undercutting etch forms a bubble recess under the active area to partially vertically isolate the active area. A the... | 12/26/2006 |
| 7154140 | Write once read only memory with large work function floating gates Structures and methods for write once read only memory employing floating gates are provided. The write once read only memory cell includes a floating gate transistor formed in a modified dynamic random access memory (DRAM) fabrication process. The floating gate tra... | 12/26/2006 |
| 7154153 | Memory device A floating gate transistor has a reduced barrier energy at an interface with an adjacent gate insulator, allowing faster charge transfer across the gate insulator at lower voltages. Data is stored as charge on the floating gate. The data charge retention time on the... | 12/26/2006 |
| 7151024 | Long retention time single transistor vertical memory gain cell A single transistor vertical memory gain cell with long data retention times. The memory cell is formed from a silicon carbide substrate to take advantage of the higher band gap energy of silicon carbide as compared to silicon. The silicon carbide provides much lowe... | 12/19/2006 |
| 7151030 | Horizontal memory devices with vertical gates Structures and methods for memory devices are provided which operate with lower control gate voltages than conventional floating gate transistors, and which do not increase the costs or complexity of the device fabrication process. The novel memory cell includes a s... | 12/19/2006 |
| 7151294 | High density stepped, non-planar flash memory A first plurality of memory cells is in a first plane in a first column of the array. A second plurality of memory cells is in a second plane in the same column. The second plurality of memory cells are coupled to the first plurality of memory cells through a series... | 12/19/2006 |
| 7151690 | 6F3-Transistor DRAM gain cell A high density vertical three transistor memory cell is provided. The high density vertical three transistor memory cell is formed in a vertical pillar. The vertical pillar includes a first vertical transfer device having a source region, a drain region, and a body ... | 12/19/2006 |
| 7149109 | Single transistor vertical memory gain cell A high density vertical single transistor gain cell is realized for DRAM operation. The gain cell includes a vertical transistor having a source region, a drain region, and a floating body region therebetween. A gate opposes the floating body region and is separated... | 12/12/2006 |
| 7148538 | Vertical NAND flash memory array Memory devices, arrays, and strings are described that facilitate the use of vertical floating gate memory cells in NAND architecture memory strings, arrays, and devices. NAND Flash memory strings, arrays, and devices in accordance with embodiments of the present in... | 12/12/2006 |
| 7141824 | Transistor with variable electron affinity gate A SiC material composition is selected to establish the barrier energy between the SIC gate and a gate insulator. Various embodiments of selected SiC material composition include a memory application, such as a flash EEPROM, and a light detector or imaging applicati... | 11/28/2006 |
| 7138681 | High density stepped, non-planar nitride read only memory A non-planar, stepped NROM array is comprised of cells formed in trenches and on pillars that are etched into a substrate. Each cell has a plurality of charge storage regions in its nitride layer and a pair of source/drain regions that are shared with adjacent cells... | 11/21/2006 |
| 7138718 | Multilevel interconnect structure with low-k dielectric A multilevel interconnect structure with a low-k dielectric constant is fabricated in an integrated circuit structure by the steps of depositing a layer of photoresist on a substrate assembly, etching the photoresist to form openings, forming a metal layer on the ph... | 11/21/2006 |
| 7135421 | Atomic layer-deposited hafnium aluminum oxide A dielectric film containing HfAlO3 and a method of fabricating such a dielectric film produce a reliable gate dielectric having an equivalent oxide thickness thinner than attainable using SiO2. A gate dielectric is formed by atomic layer depos... | 11/14/2006 |
| 7135734 | Graded composition metal oxide tunnel barrier interpoly insulators Structures and methods for programmable array type logic and/or memory devices with graded composition metal oxide tunnel barrier intergate insulators are provided. The programmable array type logic and/or memory devices include a floating gate transistor. The float... | 11/14/2006 |
