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| Number | Title | Issue Date |
| 8037285 | Trace unit An instruction processing circuit includes a decoder circuit operable to receive a sequence of instructions and to decode the received sequence of instructions into a first type of sequence of operations, and a trace builder circuit operable to receive at least a po... | 10/11/2011 |
| 7987342 | Trace unit with a decoder, a basic-block cache, a multi-block cache, and sequencer An instruction processing circuit for a processor, where the instruction processing circuit is adapted to provide one or more sequence of operations, based on one or more sequence of instructions, to an execution circuit of the processor. The instruction processing ... | 07/26/2011 |
| 7966479 | Concurrent vs. low power branch prediction An instruction processing circuit includes a decoder circuit, a basic block builder circuit, a multi-block builder circuit, first and second predictor circuits, and a sequencer circuit, where the sequencer circuit is operable, in a first environment, to cause the fi... | 06/21/2011 |
| 7953933 | Instruction cache, decoder circuit, basic block cache circuit and multi-block cache circuit An instruction processing circuit includes an instruction cache, a decoder configured to receive at least one of the instructions and to generate, based thereon, a decoder sequence of at least one operation. The circuit includes a basic block cache that includes a b... | 05/31/2011 |
| 7953961 | Trace unit with an op path from a decoder (bypass mode) and from a basic-block builder An instruction processing circuit for a processor includes a decoder circuit, a cache circuit, a sequencer circuit operable to select a next sequence of operations, and an operations fetch circuit operable to convey the next sequence of operations to an execution ci... | 05/31/2011 |
| 7949854 | Trace unit with a trace builder An instruction processing unit includes a trace builder circuit operable to (i) receive at least a portion of a first type of sequence of operations and to generate, based thereon, a second type of sequence of operations, where the portion includes at most one contr... | 05/24/2011 |
| 7676634 | Selective trace cache invalidation for self-modifying code via memory aging Selective trace cache invalidation for self-modifying code via memory aging advantageously retains some of the entries in a trace cache even during self-modifying code events. Instructions underlying trace cache entries are monitored for modification in groups, enab... | 03/09/2010 |
| 7606975 | Trace cache for efficient self-modifying code processing A trace cache for efficient self-modifying code processing enables selective invalidation of entries of the trace cache, advantageously retaining some of the entries in the trace cache even during self-modifying code events. Instructions underlying trace cache entri... | 10/20/2009 |
| 7546420 | Efficient trace cache management during self-modifying code processing Efficient trace cache management during self-modifying code processing enables selective invalidation of entries of the trace cache, advantageously retaining some of the entries in the trace cache even during self-modifying code events. Instructions underlying trace... | 06/09/2009 |
