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Mouthguard made at least partially from an edible candy
A mouthguard includes a U-shaped upper bite plate which removably fits over upper teeth of a person, with the entire upper bite plate being made from a soft, deformable and edible gummi candy.
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| Number | Title | Issue Date |
| 8319280 | Recessed access device for a memory Semiconductor memory devices having recessed access devices are disclosed. In some embodiments, a method of forming the recessed access device includes forming a device recess in a substrate material that extends to a first depth in the substrate that includes a gat... | 11/27/2012 |
| 8273619 | Methods of implanting dopant into channel regions The invention includes methods of forming channel region implants for two transistor devices simultaneously, in which a mask is utilized to block a larger percentage of a channel region location of one of the devices relative to the other. The invention also pertain... | 09/25/2012 |
| 8093643 | Multi-resistive integrated circuit memory A capacitor for use in integrated circuits comprises a layer of conductive material. The layer of conductive material including at least a first portion and a second portion, wherein the first portion and the second portion are arranged in a predetermined pattern re... | 01/10/2012 |
| 8035160 | Recessed access device for a memory Semiconductor memory devices having recessed access devices are disclosed. In some embodiments, a method of forming the recessed access device includes forming a device recess in a substrate material that extends to a first depth in the substrate that includes a gat... | 10/11/2011 |
| 7767514 | Methods of implanting dopant into channel regions The invention includes methods of forming channel region implants for two transistor devices simultaneously, in which a mask is utilized to block a larger percentage of a channel region location of one of the devices relative to the other. The invention also pertain... | 08/03/2010 |
| 7674683 | Bulk-isolated PN diode and method of forming a bulk-isolated PN diode A technique for making a bulk isolated PN diode is disclosed. In one embodiment, a method may include providing a substrate having a doped region and disposing a dielectric material over the doped region. The method may also include forming first and second holes in... | 03/09/2010 |
| 7674670 | Methods of forming threshold voltage implant regions The invention includes methods of forming channel region implants for two transistor devices simultaneously, in which a mask is utilized to block a larger percentage of a channel region location of one of the devices relative to the other. The invention also pertain... | 03/09/2010 |
| 7645671 | Recessed access device for a memory Semiconductor memory devices having recessed access devices are disclosed. In some embodiments, a method of forming the recessed access device includes forming a device recess in a substrate material that extends to a first depth in the substrate that includes a gat... | 01/12/2010 |
| 7642591 | Multi-resistive integrated circuit memory A capacitor for use in integrated circuits comprises a layer of conductive material. The layer of conductive material including at least a first portion and a second portion, wherein the first portion and the second portion are arranged in a predetermined pattern re... | 01/05/2010 |
| 7638392 | Methods of forming capacitor structures The invention includes methods of forming channel region implants for two transistor devices simultaneously, in which a mask is utilized to block a larger percentage of a channel region location of one of the devices relative to the other. The invention also pertain... | 12/29/2009 |
| 7442600 | Methods of forming threshold voltage implant regions The invention includes methods of forming channel region implants for two transistor devices simultaneously, in which a mask is utilized to block a larger percentage of a channel region location of one of the devices relative to the other. The invention also pertain... | 10/28/2008 |
| 7394142 | Bulk-isolated PN diode and method of forming a bulk-isolated PN diode A technique for making a bulk isolated PN diode. Specifically, a technique is provided for making a voltage clamp with a pair of bulk isolated PN diode. Another embodiment provides for a voltage clamp with a pair of bulk isolated PN diodes in parallel with a pair of... | 07/01/2008 |
| 7384840 | Bulk-isolated PN diode and method of forming a bulk-isolated PN diode A technique for making a bulk isolated PN diode. Specifically, a technique is provided for making a voltage clamp with a pair of bulk isolated PN diode. Another embodiment provides for a voltage clamp with a pair of bulk isolated PN diodes in parallel with a pair of... | 06/10/2008 |
| 7348652 | Bulk-isolated PN diode and method of forming a bulk-isolated PN diode A technique for making a bulk isolated PN diode. Specifically, a technique is provided for making a voltage clamp with a pair of bulk isolated PN diode. Another embodiment provides for a voltage clamp with a pair of bulk isolated PN diodes in parallel with a pair of... | 03/25/2008 |
| 7109545 | Integrated circuit memory with offset capacitor A capacitor for use in integrated circuits comprises a layer of conductive material. The layer of conductive material including at least a first portion and a second portion, wherein the first portion and the second portion are arranged in a predetermined pattern re... | 09/19/2006 |
| 7054208 | Method and device for testing a sense amp As part of a memory array, a circuit is provided for altering the drive applied to an access transistor that regulates electrical communication within the memory array. In one embodiment, the circuit is used to alter the drive applied to a sense amp's voltage-pullin... | 05/30/2006 |
| 6983404 | Method and apparatus for checking the resistance of programmable elements Method and apparatus are disclosed for checking the resistance of antifuse elements in an integrated circuit. A voltage based on the resistance of an antifuse element is compared to a voltage based on a known resistance, and an output signal is generated whose binar... | 01/03/2006 |
| 6913966 | Method for stabilizing or offsetting voltage in an integrated circuit A capacitor for use in integrated circuits comprises a layer of conductive material. The layer of conductive material including at least a first portion and a second portion, wherein the first portion and the second portion are arranged in a predetermined pattern re... | 07/05/2005 |
| 6882587 | Method of preparing to test a capacitor As part of a memory array, a circuit is provided for altering the drive applied to an access transistor that regulates electrical communication within the memory array. In one embodiment, the circuit is used to alter the drive applied to a sense amp's voltage-pullin... | 04/19/2005 |
| 6778452 | Circuit and method for voltage regulation in a semiconductor device As part of a memory array, a circuit is provided for altering the drive applied to an access transistor that regulates electrical communication within the memory array. In one embodiment, the circuit is used to alter the drive applied to a sense amp's voltage-pullin... | 08/17/2004 |
| 6690611 | Cancellation of redundant elements with a cancel bank The cancellation of a redundant element of an integrated circuit with a cancel bank is disclosed. In one embodiment, a fuse or antifuse bank is coupled to the redundant element and permanently programmed to respond to the address of a defective primary el... | 02/10/2004 |
| 6686790 | Low current redundancy anti-fuse method and apparatus A programmable circuit includes a first node and provides a programmed signal based on the state of the first node. A first anti-fuse has a programmed state and an unprogrammed state and couples the first node to a first power supply when in the programme... | 02/03/2004 |
| 6633507 | Cancellation of redundant elements with a cancel bank The cancellation of a redundant element of an integrated circuit with a cancel bank is disclosed. In one embodiment, a fuse or antifuse bank is coupled to the redundant element and permanently programmed to respond to the address of a defective primary el... | 10/14/2003 |
| 6600687 | Method of compensating for a defect within a semiconductor device As part of a memory array, a circuit is provided for altering the drive applied to an access transistor that regulates electrical communication within the memory array. In one embodiment, the circuit is used to alter the drive applied to a sense amp's vol... | 07/29/2003 |
| 6525399 | Junctionless antifuses and systems containing junctionless antifuses A method and apparatus for forming a junctionless antifuse semiconductor structure comprises forming an antifuse in non-active areas of a semiconductor wafer. In one embodiment, the antifuse is formed over a polysilicon layer, which is coupled to a field ... | 02/25/2003 |
| 6469944 | Method of compensating for a defect within a semiconductor device As part of a memory array, a circuit is provided for altering the drive applied to an access transistor that regulates electrical communication within the memory array. In one embodiment, the circuit is used to alter the drive applied to a sense amp's vol... | 10/22/2002 |
| 6462608 | Low current redundancy anti-fuse apparatus A programmable circuit includes a first node and provides a programmed signal based on the state of the first node. A first anti-fuse has a programmed state and an unprogrammed state and couples the first node to a first power supply when in the programme... | 10/08/2002 |
| 6456149 | Low current redundancy anti-fuse method and apparatus A programmable circuit includes a first node and provides a programmed signal based on the state of the first node. A first anti-fuse has a programmed state and an unprogrammed state and couples the first node to a first power supply when in the programme... | 09/24/2002 |
| 6452846 | Driver circuit for a voltage-pulling device As part of a memory array, a circuit is provided for altering the drive applied to an access transistor that regulates electrical communication within the memory array. In one embodiment, the circuit is used to alter the drive applied to a sense amp's vol... | 09/17/2002 |
| 6444558 | Methods of forming and programming junctionless antifuses A method and apparatus for forming a junctionless antifuse semiconductor structure comprises forming an antifuse in non-active areas of a semiconductor wafer. In one embodiment, the antifuse is formed over a polysilicon layer, which is coupled to a field ... | 09/03/2002 |
| 6445629 | Method of stressing a memory device As part of a memory array, a circuit is provided for altering the drive applied to an access transistor that regulates electrical communication within the memory array. In one embodiment, the circuit is used to alter the drive applied to a sense amp's vol... | 09/03/2002 |
| 6418071 | Method of testing a memory cell As part of a memory array, a circuit is provided for altering the drive applied to an access transistor that regulates electrical communication within the memory array. In one embodiment, the circuit is used to alter the drive applied to a sense amp's vol... | 07/09/2002 |
| 6410955 | Comb-shaped capacitor for use in integrated circuits A capacitor for use in integrated circuits comprises a layer of conductive material. The layer of conductive material including at least a first portion and a second portion, wherein the first portion and the second portion are arranged in a predetermined... | 06/25/2002 |
| 6353564 | Method of testing a memory array As part of a memory array, a circuit is provided for altering the drive applied to an access transistor that regulates electrical communication within the memory array. In one embodiment, the circuit is used to alter the drive applied to a sense amp's vol... | 03/05/2002 |
| 6351424 | Cancellation of redundant elements with a cancel bank The cancellation of a redundant element of an integrated circuit with a cancel bank is disclosed. In one embodiment, a fuse or antifuse bank is coupled to the redundant element and permanently programmed to respond to the address of a defective primary el... | 02/26/2002 |
| 6351140 | Low current redundancy anti-fuse method and apparatus A programmable circuit includes a first node and provides a programmed signal based on the state of the first node. A first anti-fuse has a programmed state and an unprogrammed state and couples the first node to a first power supply when in the programme... | 02/26/2002 |
| 6335888 | Margin-range apparatus for a sense amp's voltage-pulling transistor As part of a memory array, a circuit is provided for altering the drive applied to an access transistor that regulates electrical communication within the memory array. In one embodiment, the circuit is used to alter the drive applied to a sense amp's vol... | 01/01/2002 |
| 6323536 | Method and apparatus for forming a junctionless antifuse A method and apparatus for forming a junctionless antifuse semiconductor structure comprises forming an antifuse in non-active areas of a semiconductor wafer. In one embodiment, the antifuse is formed over a polysilicon layer, which is coupled to a field ... | 11/27/2001 |
| 6262927 | Current saturation test device As part of a memory array, a circuit is provided for altering the drive applied to an access transistor that regulates electrical communication within the memory array. In one embodiment, the circuit is used to alter the drive applied to a sense amp's vol... | 07/17/2001 |
| 6255894 | Low current redundancy anti-fuse method and apparatus A programmable circuit includes a first node and provides a programmed signal based on the state of the first node. A first anti-fuse has a programmed state and an unprogrammed state and couples the first node to a first power supply when in the programme... | 07/03/2001 |
