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Inventor: Jung-dal Choi


Address: Kyungki-do, KR
No. of patents: 7
Last patent issue date: 06/12/2001

NumberTitleIssue Date
6246607Methods of programming nonvolatile memory cells by floating drain or source regions associated therewith
A nonvolatile memory device in which an electrically conductive "program assist plate" is formed over the nonvolatile memory cells. Appropriate voltages are applied to the program assist plate to greatly increase the cell coupling ratio, thereby reducing ...
06/12/2001
6093605Method of manufacturing a nonvolatile memory device having a program-assist plate
A nonvolatile memory device in which an electrically conductive "program assist plate" is formed over the nonvolatile memory cells. Appropriate voltages are applied to the program assist plate to greatly increase the cell coupling ratio, thereby reducing ...
07/25/2000
5877980Nonvolatile memory device having a program-assist plate
A nonvolatile memory device in which an electrically conductive "program assist plate" is formed over the nonvolatile memory cells. Appropriate voltages are applied to the program assist plate to greatly increase the cell coupling ratio, thereby reducing ...
03/02/1999
5812454Nand-type flash memory device and driving method thereof
A NAND-type flash memory device and driving method thereof is provided. The NAND-type flash memory device includes a first and a second string, a first and a second string select line, a plurality of wordlines, and a first and a second source select line ...
09/22/1998
5751045Nand type non-volatile memory device
In a NAND type non-volatile memory device, an ion-implanting region is formed only in the source/drain region (or only in the drain region) of a depletion-type transistor for string selection, so that its junction depth is greater than that of the other t...
05/12/1998
5734609Integrated circuit memory devices having reduced susceptibility to inadvertent programming and erasure and methods of operating same
Integrated circuit memory devices having reduced susceptibility to inadvertent programming and erasure include an array of memory cells arranged as a plurality of NAND strings of EEPROM cells which share common control lines (e.g., SSL1, SSL2) and word li...
03/31/1998
5671176Semiconductor memory device including program inhibition capacitors and method for controlling program-disturb of non-selected memory cells
An integrated circuit memory device includes a plurality of wordlines, a plurality of program inhibition lines, a plurality of serially connected memory cell transistors, and a plurality of program inhibition capacitors. Each of the memory cell transistor...
09/23/1997
 
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