Did You Know...
...that the x-ray was discovered purely by accident? When German physicist Wilhelm Konrad von Roentgen was experimenting with cathode rays in 1895, he put an activated Crookes tube in a book and went out to lunch. When he returned, he discovered that a key that had also been placed in the book showed up as an image on the developed film!
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| Number | Title | Issue Date |
| 6430670 | Apparatus and method for a virtual hashed page table The present invention generally relates to an apparatus and method for efficiently translating virtual addresses utilizing either single address space or multiple address space models in a virtual memory management system. In particular, a Virtual Hash Pa... | 08/06/2002 |
| 6408373 | Method and apparatus for pre-validating regions in a virtual addressing scheme A method and apparatus pre-validate regions in a virtual addressing scheme by storing both the virtual region number (VRN) bits and region identifiers (RIDs) in translation lookaside buffer (TLB) entries. By storing both the VRN bits and RIDs in TLB entri... | 06/18/2002 |
| 6367005 | System and method for synchronizing a register stack engine (RSE) and backing memory image with a processor's execution of instructions during a state saving context switch A computer implemented method in a processor to perform a backing store switch from a first context (source context) to a second context (target context) is provided whereby the backing store memory image and RSE will be synchronized with the processor's ... | 04/02/2002 |
| 6263401 | Method and apparatus for transferring data between a register stack and a memory resource A computer-implemented method and apparatus for transferring the contents of a general register, in a register stack, to a location in a backing store in a main memory are described. When transferring the contents of a general register to a location in th... | 07/17/2001 |
| 6230248 | Method and apparatus for pre-validating regions in a virtual addressing scheme A method and apparatus pre-validate regions in a virtual addressing scheme by storing both the virtual region number (VRN) bits and region identifiers (RIDs) in translation lookaside buffer (TLB) entries. By storing both the VRN bits and RIDs in TLB entri... | 05/08/2001 |
| 6219783 | Method and apparatus for executing a flush RS instruction to synchronize a register stack with instructions executed by a processor A processor that is configured to execute a programmed flow of instructions is disclosed. The processor includes a register stack (RS). The register stack (RS) has a portion allocated for dirty registers. The processor also includes a register stack engin... | 04/17/2001 |
| 6216214 | Apparatus and method for a virtual hashed page table The present invention generally relates to an apparatus and method for efficiently translating virtual addresses utilizing either single address space or multiple address space models in a virtual memory management system. In particular, a Virtual Hash Pa... | 04/10/2001 |
| 6115777 | LOADRS instruction and asynchronous context switch A method for returning from an interrupting context to an interrupted context in a processor is disclosed. The processor executes a programmed flow of instructions. The processor includes a register stack (RS) and a register stack engine (RSE) to exchange... | 09/05/2000 |
| 6112292 | Code sequence for asynchronous backing store switch utilizing both the cover and LOADRS instructions A computer implemented method for switching from an interrupted context to an interrupting context in a processor is provided. The processor includes a register stack (RS) that has first and second portions. The processor includes a register stack engine ... | 08/29/2000 |
| 6065114 | Cover instruction and asynchronous backing store switch A computer-implemented method of switching contexts in a processor is provided. The processor includes a register stack (RS) that has first and second portions. The processor includes a register stack engine (RSE) to exchange information, in one of instru... | 05/16/2000 |
| 5940872 | Software and hardware-managed translation lookaside buffer A translation lookaside buffer (TLB) is provided including a first storage location in the TLB for storing at least a portion of a first virtual to physical memory translation. The first storage location in the TLB is both hardware-managed and software-ma... | 08/17/1999 |
| 5915117 | Computer architecture for the deferral of exceptions on speculative instructions The inventive system and method allows for software control of hardware drral of exceptions in speculative operations, and comprises three components. The first component is processor stored information which reflects the code generation strategy of appl... | 06/22/1999 |
