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A method for inducing cats to exercise consists of directing a beam of invisible light produced by a hand-held laser apparatus onto the floor or wall.
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| Number | Title | Issue Date |
| 7437499 | Dividing a flash memory operation into phases A flash memory that could not have completed an operation within a time required by a host may be able to work with the host by dividing the operation into phases that may be completed within the allocated time. As a result, a type of memory that would otherwise be ... | 10/14/2008 |
| 7200708 | Apparatus and methods for storing data which self-compensate for erase performance degradation In some embodiments, an apparatus and methods for storing data which self-compensate for erase performance degradation. Such an apparatus includes, in an exemplary embodiment, a plurality of memory blocks individually erasable during erase cycles by the application ... | 04/03/2007 |
| 6597605 | Systems with non-volatile memory bit sequence program control Systems including a bit sequence program controller to program in sequence non-volatile memory cells in an array of programmable non-volatile memory cells. The bit sequence program controller determines the bits that require programming by comparing the b... | 07/22/2003 |
| 6418059 | Method and apparatus for non-volatile memory bit sequence program controller A bit sequence program controller to program in sequence non-volatile memory cells in an array of programmable non-volatile memory cells. The bit sequence program controller determines the bits that require programming by comparing the bits of the program... | 07/09/2002 |
| 5526311 | Method and circuitry for enabling and permanently disabling test mode access in a flash memory device A method of enabling access to a test mode of a semiconductor memory in response to user commands. The method enables test mode access only when a number of "keys" are presented in the proper sequence via the memory device pins. During the first phase of ... | 06/11/1996 |
| 5410544 | External tester control for flash memory An apparatus for testing a unit comprising an internal processor coupled to a register by an internal bus. The internal processor is programmed so that it can execute an algorithm. When executed, the algorithm performs an operation on the unit. The regist... | 04/25/1995 |
