Inventor: James D. Hayden

Address: Austin, TX
No. of patents: 52
Last patent issue date: 10/24/2000

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Number	Title	Issue Date
6136678	Method of processing a conductive layer and forming a semiconductor device A method for processing a conductive layer, such as a doped polysilicon layer (14) of a gate stack, provides a degas step after precleaning to reduce particle count and defectivity. The conductive layer is provided on a substrate (10), e.g., a silicon waf...	10/24/2000
5958508	Process for forming a semiconductor device A metal-semiconductor layer (26) is formed over an insulating layer (20) such that the metal-semiconductor layer (26) is graded to have varying amounts of the semiconductor and metal throughout the layer. In one embodiment, the metal-semiconductor layer (...	09/28/1999
5824579	Method of forming shared contact structure A shared contact structure (30) is formed to electrically connect three coupling layers (59,60,46) to each other and to an active region (33) in a semiconductor substrate (31). A first coupling layer (59) and a second coupling layer (60) are formed such t...	10/20/1998
5721167	Process for forming a semiconductor device and a static-random-access memory cell A semiconductor device (10) is formed having an SRAM array with a plurality of SRAM cells. In forming the access and latch transistors, two different gate electrode compositions are used to form the access and latch transistors. More specifically, a diele...	02/24/1998
5668021	Process for fabricating a semiconductor device having a segmented channel region A process for fabricating an MOS device (44) having a segmented channel region (48) includes the fabrication of a compound MOS gate electrode (46). Both the segmented channel region (48) and the MOS gate electrode (46) are formed by creating an opening (1...	09/16/1997
5665202	Multi-step planarization process using polishing at two different pad pressures A process for polish planarizing a fill material (40) overlying a semiconductor substrate (30) includes a multi-step polishing process. In one embodiment, a second planarization layer (42) is deposited over a fill material (40) and a portion of the fill m...	09/09/1997
5624854	Method of formation of bipolar transistor having reduced parasitic capacitance Vertically stacked regions of n-type and p-type conductivity are formed around bipolar and field effect transistors to reduce parasitic capacitance between the semiconductor device and surrounding well regions. Under reverse bias a portion of the vertical...	04/29/1997
5567958	High-performance thin-film transistor and SRAM memory cell A thin-film transistor and SRAM memory cell include thin-film source and drain regions (12, 14) separated by an opening (22) and overlying and insulating layer (11). A thin-film channel layer (16) overlies the thin-film source and drain regions (12, 14) a...	10/22/1996
5543635	Thin film transistor and method of formation An under-gated thin film transistor (54) having low leakage current and a high on/off current ratio is formed using a composite layer (40) of semiconducting material. In one embodiment a composite layer (40) of semiconducting layer is formed by depositing...	08/06/1996
5510278	Method for forming a thin film transistor An under-gated thin film transistor (54) having low leakage current and a high on/off current ratio is formed using a composite layer (40) of semiconducting material. In one embodiment a composite layer (40) of semiconducting layer is formed by depositing...	04/23/1996
5504363	Semiconductor device Vertically stacked regions of n-type and p-type conductivity are formed around bipolar and field effect transistors to reduce parasitic capacitance between the semiconductor device and surrounding well regions. Under reverse bias a portion of the vertical...	04/02/1996
5498889	Semiconductor device having increased capacitance and method for making the same A semiconductor device (10) has a capacitor structure formed within an opening (30) of a stack of a dielectric layer (24), a conductive layer (26), and a dielectric layer (28). A first capacitor electrode is formed by conductive sidewall spacers (32) whic...	03/12/1996
5485420	Static-random-access memory cell and an integrated circuit having a static-random-access memory cell The present invention includes an integrated circuit having a self-aligned contact that makes contact to both a region within the substrate and a capacitor plate of a capacitor that is adjacent to the doped region. The present invention also includes a st...	01/16/1996
5473185	Static-random-access memory cell with channel stops having differing doping concentrations An SRAM cell is formed such that pass channel-stop regions, which are adjacent to the pass transistors, have a higher doping concentration compared to the latch channel-stop regions that are adjacent to the latch transistors. In one embodiment, the pass c...	12/05/1995
5459688	Semiconductor memory cell and fabrication process A semiconductor memory cell (10) includes first and second cross-coupled driver transistors (13, 19) each having a source-drain region and a channel region formed in a first thin-film layer (36, 36'). First and second parallel opposed wordlines (20, 22) o...	10/17/1995
5451543	Straight sidewall profile contact opening to underlying interconnect and method for making the same A method for making a vertical profile contact opening (18) uses an etch stop layer (14), interposed between a conductor layer (10) and a dielectric layer (16), to eliminate resputtering of the underlying conductor material which prevents tapering of the ...	09/19/1995
5418393	Thin-film transistor with fully gated channel region A semiconductor device (10) has a thin-film transistor (TFT) formed in and around an opening (24) in a dielectric layer (22). A conductive layer (26) lines the opening sidewalls and serves as a gate electrode of the transistor. A conductive layer (30) is ...	05/23/1995
5413948	Method for forming a dual transistor structure A transistor structure (10) has a substrate (12). A first transistor is formed within the substrate (12) having a source region (38), a drain region (30), and a gate electrode formed by a first spacer (26a). A second transistor is formed within the substr...	05/09/1995
5407847	Method for fabricating a semiconductor device having a shallow doped region A method is provided for the formation of ultra-shallow boron doped regions in a semiconductor device. In one embodiment of the invention an N-type semiconductor substrate (15) is provided having a first P-type region formed therein. A dielectric layer (1...	04/18/1995
5408130	Interconnection structure for conductive layers An interconnect structure is formed having a substrate (10). A conductive layer (14) is formed overlying the substrate (10). A conductive layer (18) is formed overlying the conductive layer (14). An opening (19) is etched through the conductive layer (18)...	04/18/1995
5405806	Method for forming a metal silicide interconnect in an integrated circuit A metal silicide interconnect (48, 92, 124) is formed in an integrated circuit using a sacrificial layer (30, 78, 108). In one embodiment a sacrificial layer of titanium nitride (30) is formed overlying a semiconductor substrate (12) and a polysilicon con...	04/11/1995
5398200	Vertically formed semiconductor random access memory device A semiconductor memory device is formed having a substrate (12). A diffusion (14) is formed within the substrate (12). A first vertical transistor stack (122) is formed. A second vertical transistor stack (124) is formed. The first vertical transistor sta...	03/14/1995
5393689	Process for forming a static-random-access memory cell An SRAM cell is formed such that pass channel-stop regions, which are adjacent to the pass transistors, have a higher doping concentration compared to the latch channel-stop regions that are adjacent to the latch transistors. In one embodiment, the pass c...	02/28/1995
5376562	Method for forming vertical transistor structures having bipolar and MOS devices A transistor is formed as either a bipolar transistor (10) or an MOS transistor (11). Each transistor (10 or 11) has a substrate (12). Bipolar transistor (10) has a first current electrode (26) underlying a control electrode (28), and a second current ele...	12/27/1994
5377139	Process forming an integrated circuit The present invention includes an integrated circuit having a self-aligned contact that makes contact to both a region within the substrate and a capacitor plate of a capacitor that is adjacent to the doped region. The present invention also includes a st...	12/27/1994
5374573	Method of forming a self-aligned thin film transistor A thin film transistor with self-aligned source and drain regions is fabricated, in one embodiment, by forming an opening (124) in a dielectric layer (118) which overlies a substrate (116). A semiconductive sidewall spacer (130) is formed around the perim...	12/20/1994
5373170	Semiconductor memory device having a compact symmetrical layout A semiconductor memory cell (10) having a symmetrical layout is fabricated in first and second active regions (44, 46) of a semiconductor substrate (11). A first driver transistor (16) resides in the second active region (46), and a second driver transist...	12/13/1994
5371026	Method for fabricating paired MOS transistors having a current-gain differential A semiconductor device (10) and process provides first and second, electrically coupled MOS transistors (14, 16) in which the current gain of the second MOS transistor (16) is greater than the current gain of the first MOS transistor (14). First and secon...	12/06/1994
5348903	Process for fabricating a semiconductor memory cell having thin-film driver transistors overlapping dual wordlines A semiconductor memory cell (10) includes first and second cross-coupled driver transistors (13, 19) each having a source-drain region and a channel region formed in a first thin-film layer (36, 36'). First and second parallel opposed wordlines (20, 22) o...	09/20/1994
5334861	Semiconductor memory cell A semiconductor memory cell (10) including cross coupled CMOS transistors (12, 14) wherein an N-channel transistor (20) overlies a central portion of each of a first and second active regions (13, 13') at a position intermediate to two word lines (40, 42)...	08/02/1994
5330929	Method of making a six transistor static random access memory cell The present invention includes a static random access memory cell and a method of forming the memory cell, wherein the memory cell may comprise an active region and a first layer. The active region including a first segment, a second segment, and a third ...	07/19/1994
5324960	Dual-transistor structure and method of formation A transistor structure (10) has a substrate (12). A first transistor is formed within the substrate (12) having a source region (38), a drain region (30), and a gate electrode formed by a first spacer (26a). A second transistor is formed within the substr...	06/28/1994
5308782	Semiconductor memory device and method of formation A semiconductor memory device is formed having a substrate (12). A diffusion (14) is formed within the substrate (12). A first vertical transistor stack (122) is formed. A second vertical transistor stack (124) is formed. The first vertical transistor sta...	05/03/1994
5308997	Self-aligned thin film transistor A thin film transistor with self-aligned source and drain regions is fabricated, in one embodiment, by forming an opening (124) in a dielectric layer (118) which overlies a substrate (116). A semiconductive sidewall spacer (130) is formed around the perim...	05/03/1994
5291053	Semiconductor device having an overlapping memory cell A semiconductor device having an overlapping memory cell (10), which includes a split wordline configuration and intersects at least a portion of the driver gate electrodes with each wordline. In one embodiment, a semiconductor substrate (11) has first an...	03/01/1994
5279976	Method for fabricating a semiconductor device having a shallow doped region A method is provided for the formation of ultra-shallow boron doped regions in a semiconductor device. In one embodiment of the invention an N-type semiconductor substrate (15) is provided having a first P-type region formed therein. A dielectric layer (1...	01/18/1994
5275964	Method for compactly laying out a pair of transistors A pair of first and second thin film transistors (TFTs). The transistors are formed from a first continuous, conductive region (38) and a second continuous, conductive region (39) which underlies the first conductive region (38). The first transistor has ...	01/04/1994
5262352	Method for forming an interconnection structure for conductive layers An interconnect structure is formed having a substrate (10). A conductive layer (14) is formed overlying the substrate (10). A conductive layer (18) is formed overlying the conductive layer (14). An opening (19) is etched through the conductive layer (18)...	11/16/1993
5252849	Transistor useful for further vertical integration and method of formation A transistor is formed as either a bipolar transistor (10) or an MOS transistor (11). Each transistor (10 or 11) has a substrate (12). Bipolar transistor (10) has a first current electrode (26) underlying a control electrode (28), and a second current ele...	10/12/1993
5243203	Compact transistor pair layout and method thereof A pair of first and second thin film transistors (TFTs). The transistors are formed from a first continuous, conductive region (38) and a second continuous, conductive region (39) which underlies the first conductive region (38). The first transistor has ...	09/07/1993

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