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Patent No. 5823572

Self Defense Weapon With Memo

A self defense weapon formed as a memo pad and which is easily held by a person's fingers, therefore making it possible to provide protection from a mugger and also to quickly and easily write a record or a message without failure of missing or forgetting significant information under a stressful situation.

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Inventor: Hiroyuki Yamane


Address: Anjo, JP
No. of patents: 9
Last patent issue date: 06/21/2005

NumberTitleIssue Date
6908857Method of manufacturing semiconductor device
A method for manufacturing a semiconductor device having on a silicon substrate semiconductor elements and aluminum (Al) alloy wiring leads as electrically connected thereto is disclosed. The method includes the steps of forming on the silicon substrate an Al alloy ...
06/21/2005
6650017Electrical wiring of semiconductor device enabling increase in electromigration (EM) lifetime
A method for manufacturing a semiconductor device having on a silicon substrate semiconductor elements and aluminum (Al) alloy wiring leads as electrically connected thereto is disclosed. The method includes the steps of forming on the silicon substrate a...
11/18/2003
6348735Electrode for semiconductor device and method for manufacturing same
The purpose of the present invention is to obtain an electrode wiring structure for semiconductor devices that can suppress the occurrence of Al voids inside aluminum alloy wiring without regard to the orientation of such aluminum alloy wiring. An interla...
02/19/2002
6337249Semiconductor device and fabrication process thereof
A semiconductor device having an enhancement-type MOS structure which can prevent large leakage current is disclosed. A high-concentration region for threshold-value regulation use formed in a channel region below a gate electrode in an enhancement-type t...
01/08/2002
6066891Electrode for semiconductor device including an alloy wiring layer for reducing defects in an aluminum layer and method for manufacturing the same
The purpose of the present invention is to obtain an electrode wiring structure for semiconductor devices that can suppress the occurrence of Al voids inside aluminum alloy wiring without regard to the orientation of such aluminum alloy wiring. An interla...
05/23/2000
5675167Enhancement-type semiconductor having reduced leakage current
A semiconductor device having an enhancement-type MOS structure which can prevent large leakage current is disclosed. A high-concentration region for threshold-value regulation use formed in a channel region below a gate electrode in an enhancement-type t...
10/07/1997
5342802Method of manufacturing a complementary MIS transistor
A high withstanding voltage MIS transistor, including an offset region and a double offset region in a region of a semiconductor substrate. The region of the semiconductor substrate has a first conductivity type. The offset region connects to a drain regi...
08/30/1994
5216272High withstanding voltage MIS transistor
A high withstanding voltage MIS transistor, including an offset region and a double offset region in a region of a semiconductor substrate. The region of the semiconductor substrate has a first conductivity type. The offset region connects to a drain regi...
06/01/1993
5036019Method of producing a complementary-type semiconductor device
A method of producing a MIS transistor such as a MOS transistor has a P type and an N type channel transistors. P type and N type well regions are provided with the N type and the P type channel transistors, respectively. Both the P type and the N type we...
07/30/1991
 
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