Inventor: Guy Lynn Guthrie

Address: Austin, TX
No. of patents: 195
Last patent issue date: 01/08/2013

Number	Title	Issue Date
8352712	Method and system for specualtively sending processor-issued store operations to a store queue with full signal asserted A method and processor chip design for enabling a processor core to continue sending store operations speculatively to the store queue after the core receives indication that the store queue is full. The processor core is configured with speculative store logic that...	01/08/2013
8281075	Processor system and methods of triggering a block move using a system bus write command initiated by user code A technique for triggering a system bus write command with user code includes identifying a specific store-type instruction in a user instruction sequence. The specific store-type instruction is converted into a specific request-type command, which is configured to ...	10/02/2012
8230178	Data processing system and method for efficient coherency communication utilizing coherency domain indicators In a cache coherent data processing system including at least first and second coherency domains, a memory block is stored in a system memory in association with a domain indicator indicating whether or not the memory block is cached, if at all, only within the firs...	07/24/2012
8230117	Techniques for write-after-write ordering in a coherency managed processor system that employs a command pipeline A technique for maintaining input/output (I/O) command ordering on a bus includes assigning a channel identifier to I/O commands of an I/O stream. In this case, the channel identifier indicates the I/O commands belong to the I/O stream. A command location indicator ...	07/24/2012
8214600	Data processing system and method for efficient coherency communication utilizing coherency domains In a cache coherent data processing system including at least first and second coherency domains, a master performs a first broadcast of an operation within the cache coherent data processing system that is limited in scope of transmission to the first coherency dom...	07/03/2012
8195880	Information handling system with immediate scheduling of load operations in a dual-bank cache with dual dispatch into write/read data flow An information handling system (IHS) includes a processor with a cache memory system. The processor includes a processor core with an L1 cache memory that couples to an L2 cache memory. The processor includes an arbitration mechanism that controls load and store req...	06/05/2012
8166246	Chaining multiple smaller store queue entries for more efficient store queue usage A computer implemented method, a processor chip, a data processing system, and computer program product in a data processing system process information in a store cache of a data processing system. The store cache receives a first entry that includes a first address...	04/24/2012
8140759	Specifying an access hint for prefetching partial cache block data in a cache hierarchy A system and method for specifying an access hint for prefetching only a subsection of cache block data, for more efficient system interconnect usage by the processor core. A processing unit receives a data cache block touch (DCBT) instruction containing an access h...	03/20/2012
8140765	Information handling system with immediate scheduling of load operations in a dual-bank cache with single dispatch into write/read data flow An information handling system (IHS) includes a processor with a cache memory system. The processor includes a processor core with an L1 cache memory that couples to an L2 cache memory. The processor includes an arbitration mechanism that controls load and store req...	03/20/2012
8140756	Information handling system with immediate scheduling of load operations and fine-grained access to cache memory An information handling system (IHS) includes a processor with a cache memory system. The processor includes a processor core with an L1 cache memory that couples to an L2 cache memory. The processor includes an arbitration mechanism that controls load and store req...	03/20/2012
8015358	System bus structure for large L2 cache array topology with different latency domains A cache memory which loads two memory values into two cache lines by receiving separate portions of a first requested memory value from a first data bus over a first time span of successive clock cycles and receiving separate portions of a second requested memory va...	09/06/2011
8001330	L2 cache controller with slice directory and unified cache structure A cache memory logically partitions a cache array having a single access/command port into at least two slices, and uses a first directory to access the first array slice while using a second directory to access the second array slice, but accesses from the cache di...	08/16/2011
7987320	Cache mechanism and method for avoiding cast out on bad victim select and recycling victim select operation A method, apparatus, and computer for identifying selection of a bad victim during victim selection at a cache and recovering from such bad victim selection without causing the system to crash or suspend forward progress of the victim selection process. Among the ba...	07/26/2011
7849298	Enhanced processor virtualization mechanism via saving and restoring soft processor/system states A method and system are disclosed for saving soft state information, which is non-critical for executing a process in a processor, upon a receipt of a process interrupt by the processor. The soft state is transmitted to a memory associated with the processor via a m...	12/07/2010
7827354	Victim cache using direct intervention A method, system, and device for enabling intervention across same-level cache memories. In a preferred embodiment, responsive to a cache miss in a first cache memory a direct intervention request is sent from the first cache memory to a second cache memory requesti...	11/02/2010
7793048	System bus structure for large L2 cache array topology with different latency domains A cache memory which loads two memory values into two cache lines by receiving separate portions of a first requested memory value from a first data bus over a first time span of successive clock cycles and receiving separate portions of a second requested memory va...	09/07/2010
7783834	L2 cache array topology for large cache with different latency domains A cache memory logically associates a cache line with at least two cache sectors of a cache array wherein different sectors have different output latencies and, for a load hit, selectively enables the cache sectors based on their latency to output the cache line ove...	08/24/2010
7783842	Cache coherent I/O communication A processing unit includes a processor core, an input/output (I/O) communication adapter coupled to the processor core, and a cache system coupled to the processor core and to the I/O communication adapter. The cache system including a cache array, a cache directory...	08/24/2010
7783841	Efficient coherency communication utilizing an IG coherency state A cache coherent data processing system includes at least first and second coherency domains each including at least one processing unit and a cache memory. The cache memory includes a cache controller, a data array including a data storage location for caching a me...	08/24/2010
7774555	Data processing system and method for efficient coherency communication utilizing coherency domain indicators In a cache coherent data processing system including at least first and second coherency domains, a memory block is stored in a system memory in association with a domain indicator indicating whether or not the memory block is cached, if at all, only within the firs...	08/10/2010
7689777	Cache member protection with partial make MRU allocation A method and apparatus for enabling protection of a particular member of a cache during LRU victim selection. LRU state array includes additional “protection” bits in addition to the state bits. The protection bits serve as a pointer to identify the location of ...	03/30/2010
7617378	Multiprocessor system with retry-less TLBI protocol A symmetric multiprocessor data processing system (SMP) that implements a TLBI protocol, which enables multiple TLBI operations from multiple processors to complete without causing delay. Each processor includes a TLBI register associated with the TLB and TLBI logic...	11/10/2009
7584329	Data processing system and method for efficient communication utilizing an Ig coherency state A cache coherent data processing system includes at least first and second coherency domains each including at least one processing unit and a cache memory. The cache memory includes a cache controller, a data array including a data storage location for caching a me...	09/01/2009
7533227	Method for priority scheduling and priority dispatching of store conditional operations in a store queue A method, system, and processor chip design for reducing the latency between completing a LARX operation and receiving the associated STCX operation to complete the update to the cache line. Each entry of the store queue of the issuing processor is provided an addit...	05/12/2009
7500065	Data processing system and method for efficient L3 cache directory management A system and method for cache management in a data processing system having a memory hierarchy of upper memory and lower memory cache. A lower memory cache controller accesses a coherency state table to determine replacement policies of coherency states for cache li...	03/03/2009
7493446	System and method for completing full updates to entire cache lines stores with address-only bus operations A method and processor system that substantially eliminates data bus operations when completing updates of an entire cache line with a full store queue entry. The store queue within a processor chip is designed with a series of AND gates connecting individual bits o...	02/17/2009
7493478	Enhanced processor virtualization mechanism via saving and restoring soft processor/system states A method and system are disclosed for saving soft state information, which is non-critical for executing a process in a processor, upon a receipt of a process interrupt by the processor. The soft state is transmitted to a memory associated with the processor via a m...	02/17/2009
7490200	L2 cache controller with slice directory and unified cache structure A cache memory logically partitions a cache array having a single access/command port into at least two slices, and uses a first cache directory to access the first cache array slice while using a second cache directory to access the second cache array slice, but ac...	02/10/2009
7490202	Data processing system and method for efficient L3 cache directory management A system and method for cache management in a data processing system having a memory hierarchy of upper memory and lower memory cache. A lower memory cache controller accesses a coherency state table to determine replacement policies of coherency states for cache li...	02/10/2009
7480772	Data processing system and method for efficient communication utilizing an Tn and Ten coherency states A cache coherent data processing system includes at least first and second coherency domains each including at least one processing unit. The first coherency domain includes a first cache memory and a second cache memory, and the second coherency domain includes a r...	01/20/2009
7469322	Data processing system and method for handling castout collisions A data processing system includes a memory controller of a system memory that receives first and second castout operations both specifying a same address. In response to receiving said first and second castout operations, the memory controller performs a single upda...	12/23/2008
7469318	System bus structure for large L2 cache array topology with different latency domains A cache memory which loads two memory values into two cache lines by receiving separate portions of a first requested memory value from a first data bus over a first time span of successive clock cycles and receiving separate portions of a second requested memory va...	12/23/2008
7454577	Data processing system and method for efficient communication utilizing an Tn and Ten coherency states A cache coherent data processing system includes at least first and second coherency domains each including at least one processing unit. The first coherency domain includes a first cache memory and a second cache memory, and the second coherency domain includes a r...	11/18/2008
7401189	Pipelining D states for MRU steerage during MRU/LRU member allocation A method and apparatus for preventing selection of Deleted (D) members as an LRU victim during LRU victim selection. During each cache access targeting the particular congruence class, the deleted cache line is identified from information in the cache directory. A l...	07/15/2008
7366841	L2 cache array topology for large cache with different latency domains A cache memory logically associates a cache line with at least two cache sectors of a cache array wherein different sectors have different output latencies and, for a load hit, selectively enables the cache sectors based on their latency to output the cache line ove...	04/29/2008
7366844	Data processing system and method for handling castout collisions A data processing system includes a memory controller of a system memory that receives first and second castout operations both specifying a same address. In response to receiving said first and second castout operations, the memory controller performs a single upda...	04/29/2008
7363433	Cache member protection with partial make MRU allocation A method and apparatus for enabling protection of a particular member of a cache during LRU victim selection. LRU state array includes additional “protection” bits in addition to the state bits. The protection bits serve as a pointer to identify the location of ...	04/22/2008
7360041	Method for priority scheduling and priority dispatching of store conditional operations in a store queue A method, system, and processor chip design for reducing the latency between completing a LARX operation and receiving the associated STCX operation to complete the update to the cache line. Each entry of the store queue of the issuing processor is provided an addit...	04/15/2008
7360021	System and method for completing updates to entire cache lines with address-only bus operations A method and processor system that substantially eliminates data bus operations when completing updates of an entire cache line with a full store queue entry. The store queue within a processor chip is designed with a series of AND gates connecting individual bits o...	04/15/2008
7343455	Cache mechanism and method for avoiding cast out on bad victim select and recycling victim select operation A method, apparatus, and computer for identifying selection of a bad victim during victim selection at a cache and recovering from such bad victim selection without causing the system to crash or suspend forward progress of the victim selection process. Among the ba...	03/11/2008

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Inventor: Guy Lynn Guthrie