Inventor: Gurtej S. Sandhu

Address: Boise, ID
No. of patents: 742
Last patent issue date: 01/29/2013

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Number	Title	Issue Date
8362546	Cross-point diode arrays and methods of manufacturing cross-point diode arrays Methods of forming an array of memory cells and memory cells that have pillars. Individual pillars can have a semiconductor post formed of a bulk semiconductor material and a sacrificial cap on the semiconductor post. Source regions can be between columns of the pil...	01/29/2013
8361328	Nanotube separation methods A nanotube separation method includes depositing a tag on a nanotube in a nanotube mixture. The nanotube has a defect and the tag deposits at the defect where a deposition rate is greater than on another nanotube in the mixture lacking the defect. The method include...	01/29/2013
8362576	Transistor with reduced depletion field width Atomic layer deposition is enhanced using plasma. Plasma begins prior to flowing a second precursor into a chamber. The second precursor reacts with a first precursor to deposit a layer on a substrate. The layer may include at least one element from each of the firs...	01/29/2013
8358534	Spin torque transfer memory cell structures and methods Spin Torque Transfer (STT) memory cell structures and methods are described herein. One or more STT memory cell structures include a tunneling barrier material positioned between a ferromagnetic storage material and a pinned ferromagnetic material in contact with an...	01/22/2013
8357970	Multi-level charge storage transistors and associated methods Methods of fabricating charge storage transistors are described, along with apparatus and systems that include them. In one such method, a pillar of epitaxial silicon is formed. At least first and second charge storage nodes (e.g., floating gates) are formed around ...	01/22/2013
8324107	Method for forming high density patterns Methods are disclosed, such as those involving increasing the density of isolated features in an integrated circuit. In one or more embodiments, a method is provided for forming an integrated circuit with a pattern of isolated features having a final density of isol...	12/04/2012
8324065	Resistive memory and methods of processing resistive memory Resistive memory and methods of processing resistive memory are described herein. One or more method embodiments of processing resistive memory include conformally forming a cell material in an opening in an interlayer dielectric such that a seam is formed in the ce...	12/04/2012
8323995	Diodes, and methods of forming diodes Some embodiments include methods of forming diodes. The methods may include oxidation of an upper surface of a conductive electrode to form an oxide layer over the conductive electrode. In some embodiments, the methods may include formation of an oxidizable material...	12/04/2012
8310868	Spin torque transfer memory cell structures and methods Spin Torque Transfer (STT) memory cell structures and methods are described herein. One or more STT memory cell structures comprise a STT stack including: a pinned ferromagnetic material in contact with an antiferromagnetic material; a tunneling barrier material pos...	11/13/2012
8304353	Silicon dioxide deposition methods using at least ozone and TEOS as deposition precursors Embodiments disclosed herein pertain to silicon dioxide deposition methods using at least ozone and tetraethylorthosilicate (TEOS) as deposition precursors. In one embodiment, a silicon dioxide deposition method using at least ozone and TEOS as deposition precursors...	11/06/2012
8300454	Spin torque transfer memory cell structures and methods Spin Torque Transfer (STT) memory cell structures and methods are described herein. One or more STT memory cell structures include a tunneling barrier material positioned between a ferromagnetic storage material and a pinned ferromagnetic material in contact with an...	10/30/2012
8288818	Devices with nanocrystals and methods of formation Devices can be fabricated using a method of growing nanoscale structures on a semiconductor substrate. According to various embodiments, nucleation sites are created on a surface of the substrate. The creation of the nucleation sites includes implanting ions with an...	10/16/2012
8282999	Spin-on film processing using acoustic radiation pressure An apparatus and process operate to impose sonic pressure upon a spin-on film liquid mass that exhibits a liquid topography and in a solvent vapor overpressure to alter the liquid topography. Other apparatus and processes are disclosed. ...	10/09/2012
8278167	Method and structure for integrating capacitor-less memory cell with logic Methods for fabricating integrated circuits include fabricating a logic device on a substrate, forming an intermediate semiconductor substrate on a surface of the logic device, and fabricating a capacitor-less memory cell on the intermediate semiconductor substrate....	10/02/2012
8273643	Diodes, and methods of forming diodes Some embodiments include methods of forming diodes in which a first electrode is formed to have a pedestal extending upwardly from a base. At least one layer is deposited along an undulating topography that extends across the pedestal and base, and a second electrod...	09/25/2012
8273634	Methods of fabricating substrates A method of fabricating a substrate includes forming first and second spaced features over a substrate. The first spaced features have elevationally outermost regions which are different in composition from elevationally outermost regions of the second spaced featur...	09/25/2012
8268692	Non-volatile memory cell devices and methods A method of fabricating a memory cell including forming nanodots over a first dielectric layer and forming an intergate dielectric layer over the nanodots, where the intergate dielectric layer encases the nanodots. To form sidewalls of the memory cell, a portion of ...	09/18/2012
8268543	Methods of forming patterns on substrates A method of forming a pattern on a substrate includes forming spaced first features over a substrate. The spaced first features have opposing lateral sidewalls. Material is formed onto the opposing lateral sidewalls of the spaced first features. That portion of such...	09/18/2012
8256695	Method for purification of semiconducting single wall nanotubes A process of forming a semiconductive carbon nanotube structure includes imposing energy on a mixture that contains metallic carbon nanotubes and semiconductive carbon nanotubes under conditions to cause the metallic carbon nanotubes to be digested or to decompose s...	09/04/2012
8258034	Charge-trap based memory Methods of fabricating 3D charge-trap memory cells are described, along with apparatus and systems that include them. In a planar stack formed by alternate layers of electrically conductive and insulating material, a substantially vertical opening may be formed. Ins...	09/04/2012
8247302	Methods of fabricating substrates A method of fabricating a substrate includes forming spaced first features and spaced second features over a substrate. The first and second features alternate with one another and are spaced relative one another. Width of the spaced second features is laterally tri...	08/21/2012
8227313	One-transistor composite-gate memory One-transistor memory devices facilitate nonvolatile data storage through the manipulation of oxygen vacancies within a trapping layer of a field-effect transistor (FET), thereby providing control and variation of threshold voltages of the transistor. Various thresh...	07/24/2012
8228730	Memory cell structures and methods Memory cell structures and methods are described herein. One or more memory cells include a transistor having a charge storage node, a dielectric material positioned between the charge storage node and a channel region of the transistor, the channel region positione...	07/24/2012
8223539	GCIB-treated resistive device The present disclosure includes GCIB-treated resistive devices, devices utilizing GCIB-treated resistive devices (e.g., as switches, memory cells), and methods for forming the GCIB-treated resistive devices. One method of forming a GCIB-treated resistive device incl...	07/17/2012
8222127	Methods of forming structures having nanotubes extending between opposing electrodes and structures including same A semiconductor structure including nanotubes forming an electrical connection between electrodes is disclosed. The semiconductor structure may include an open volume defined by a lower surface of an electrically insulative material and sidewalls of at least a porti...	07/17/2012
8207563	Integrated circuitry A method of forming a plurality of capacitors includes providing a plurality of capacitor electrodes comprising sidewalls. The plurality of capacitor electrodes are supported at least in part with a retaining structure which engages the sidewalls, with the retaining...	06/26/2012
8207570	Semiconductor constructions Some embodiments include formation of polymer spacers along sacrificial material, removal of the sacrificial material, and utilization of the polymer spacers as masks during fabrication of integrated circuitry. The polymer spacer masks may, for example, be utilized ...	06/26/2012
8207557	Cross-point memory structures Some embodiments include cross-point memory structures. The structures may include a line of first electrode material extending along a first horizontal direction, a multi-sided container of access device materials over the first electrode material, a memory element...	06/26/2012
8207016	Methods of cooling semiconductor dies The invention includes semiconductor packages having grooves within a semiconductor die backside; and includes semiconductor packages utilizing carbon nanostructures (such as, for example, carbon nanotubes) as thermally conductive interface materials. The invention ...	06/26/2012
8198172	Methods of forming integrated circuits using donor and acceptor substrates Methods for fabricating integrated circuit devices on an acceptor substrate devoid of circuitry are disclosed. Integrated circuit devices are formed by sequentially disposing one or more levels of semiconductor material on an acceptor substrate, and fabricating circ...	06/12/2012
8199556	Methods of reading and using memory cells Some embodiments include methods of reading memory cells. The memory cells have a write operation that occurs only if a voltage of sufficient absolute value is applied for a sufficient duration of time; and the reading is conducted with a pulse that is of too short ...	06/12/2012
8173034	Methods of utilizing block copolymer to form patterns Some embodiments include methods of utilizing block copolymer to form patterns between weirs. The methods may utilize liners along surfaces of the weirs to compensate for partial-width segments of the patterns in regions adjacent the weirs. Some embodiments include ...	05/08/2012
8174061	Floating-gate structure with dielectric component Floating-gate memory cells having a floating gate with a conductive portion and a dielectric portion facilitate increased levels of charge trapping sites within the floating gate. The conductive portion includes a continuous component providing bulk conductivity to ...	05/08/2012
8163355	Formation of carbon-containing material A method includes forming ionic clusters of carbon-containing molecules, which molecules have carbon-carbon sp2 bonds, and accelerating the clusters. A surface of a substrate is irradiated with the clusters. A material is formed on the surface using the c...	04/24/2012
8164081	Memory devices and formation methods A method includes forming an electrical insulator material over an integrated circuit having a metal-containing conductive interconnect and activating a dopant in a semiconductor material of a substrate to provide a doped region. The doped region provides a junction...	04/24/2012
8148222	Cross-point diode arrays and methods of manufacturing cross-point diode arrays Methods of forming an array of memory cells and memory cells that have pillars. Individual pillars can have a semiconductor post formed of a bulk semiconductor material and a sacrificial cap on the semiconductor post. Source regions can be between columns of the pil...	04/03/2012
8133664	Methods of forming patterns Some embodiments include methods of forming patterns of openings. The methods may include forming spaced features over a substrate. The features may have tops and may have sidewalls extending downwardly from the tops. A first material may be formed along the tops an...	03/13/2012
8129289	Method to deposit conformal low temperature SiO2 Methods of controlling critical dimensions of reduced-sized features during semiconductor fabrication through pitch multiplication are disclosed. Pitch multiplication is accomplished by patterning mask structures via conventional photoresist techniques and subsequen...	03/06/2012
8114573	Topography based patterning A mask having features formed by self-organizing material, such as diblock copolymers, is formed on a partially fabricated integrated circuit. Initially, a copolymer template, or seed layer, is formed on the surface of the partially fabricated integrated circuit. To...	02/14/2012
8093658	Electronic device with asymmetric gate strain The use of strained gate electrodes in integrated circuits results in a transistor having improved carrier mobility, improved drive characteristics, and reduced source drain junction leakage. The gate electrode strain can be obtained through non symmetric placement ...	01/10/2012

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Inventor: Gurtej S. Sandhu